Silicon Laboratories Inc.

Skyworks Solutions, Inc.

Stefan N Mastovich

Krishna Pentakota

Mohammad Al-Shyoukh

Ion Constantin Tesu

James Edward Heckroth

Dan Bernard Kasha

Douglas S Piasecki

Thomas Saroshan David

Russell Croman

Timothy Thomas Rueger

John Nathaniel Wilson

Huanhui Zhan

Jia-Hau Liu

Thomas C Fowler

Michael Ireland

Greg Ridsdale

Ernest T Stroud

Lyric Jackson

Tamás Marozsák

András Vince Horváth

Joselyn Torres-Torres

Long Van Nguyen

A method for controlling a high-power drive device includes providing a current having a first predetermined current level to an output node during a first phase of a multi-phase turn-on process for the high-power drive device coupled to the output node. The method includes transitioning from the first phase to a second phase of the multi-phase turn-on process based on a first indication of a sensed voltage level on the output node during the first phase and a second indication of a time elapsed from a start of the first phase during the first phase. The method includes providing the current having a second predetermined current level to the output node during the second phase.

Variable current drive for isolated gate drivers

A technique for powering gate drivers in a half-bridge configuration uses a single external power supply to power each gate driver. A single on-chip regulator regulates the positive turn-on voltage for each switch. The regulator overhead, is also used as the negative voltage for turn-off, thus transferring the low-frequency variation of the external power supply to the negative turn-off voltage. Accordingly, a single on-chip regulator generates both the positive turn-on voltage and the negative turn-off voltage. In at least one embodiment, reuse of the switch turn-off current further reduces on-chip power dissipation. The on-chip regulator's output filter capacitor discharges during turn-on of the external power switching device. During turn-off, the current that discharges the switch gate capacitance recharges the regulator filter capacitor.

Generation of positive and negative switch gate control voltages

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

High dielectric constant material at locations of high fields

A method for driving a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. The method includes providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process. The method includes transitioning from the first phase to the second phase based on the first indication and the second indication. A multi-die, distributed package technique addresses power dissipation requirements for a driver product based on size and associated power dissipation needs of the high-power drive device in a target application.

A power transfer device includes a first power supply node, a second power supply node, and an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal. The oscillator circuit includes a regulated power supply node and an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level. The clamped voltage level is linearly related to a first voltage level on the first power supply node.

Power resonator with wide input voltage range for isolated power transfer

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

Single pin test interface for pin limited systems

A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Power transfer device using an oscillator

An integrated circuit includes an input terminal configured to receive an input signal, a reference voltage node configured to provide a control voltage, and a pass transistor comprising a first terminal coupled to a first node, a control terminal coupled to the reference voltage node, and a second terminal coupled to the input terminal. The control voltage has a control voltage level sufficient to allow a signal to pass from the second terminal to the first terminal. The pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of the input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signal to the first node in response to the voltage level being above the first voltage level. At most, a negligible DC current flows through the input terminal into the second terminal.

Wide voltage range input interface

An isolation system includes a transmit die and a receive die coupled by an isolation channel. The transmit die receives diagnostic data at an input terminal and transmits the diagnostic data over an isolation channel to a receive die. The receive die supplies a signal from an internal node in the receive die identified by the diagnostic data to an output terminal of the receive die. Other diagnostic data received by the transmit die causes the transmit die to supply a signal from an internal node in the transmit die to a terminal of the transmit die.

Test interface with access across isolation barrier

A technique for attenuating common mode transient events uses a differential receiver circuit including a band-stop filter having a stopband faround a notch frequency fof a received signal. The differential receiver circuit includes a first high-pass filter coupled in series with the band-stop filter. The notch frequency fis less than a carrier frequency fof a signal received by the differential receiver circuit. The band-stop filter may include a buffer circuit and a notch filter coupled in series with the buffer circuit. The notch filter may have a second stopband around the notch frequency f. The differential receiver circuit may have a propagation delay that is independent of a pulse width of common mode transient energy attenuated by the differential receiver circuit.

Receiver architecture for digital isolators employing notch filters common mode transient immunity

An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

Isolated power transfer with integrated transformer and voltage control

An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.

System and method for LCD loop control

An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage.

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Round Rock, TX, United States of America

Stefan N Mastovich