Infineon Technologies Ag

Stefan Martens

Horst Theuss

Ulrich Krumbein

Mathias Vaupel

Helmut Wietschorke

Tze Yang Hin

Daniel Kehrer

Beng Keh See

Chau Fatt Chiang

Swee Kah Lee

Adolf Koller

Kok Yau Chua

Werner Simbuerger

Matthias Steiert

Berthold Schuderer

Mei Chin Ng

Sook Woon Chan

Raimund Peichl

Sebastian Bernrieder

Beng-Keh See

Hock Siang Chua

Kian Hong Yeo

A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Module and method of manufacturing a module

A semiconductor package includes an electrically conductive lead-frame, including a first die paddle having a first opening, and a plurality of electrically conductive leads, a ridge formed around a perimeter of the first opening, and an electrically insulating molding compound. The electrically insulating molding compound includes an interior cavity being defined by a planar base surface and outer sidewalls, a second opening formed in the base surface, and an interior sidewall within the interior cavity. The molding compound is formed around the lead-frame with the first die paddle in the interior cavity. The first and second openings are aligned with one another so as to form a port that provides access to the interior cavity. The ridge and the interior sidewall form a dam that is configured to collect liquefied sealant and prevent the liquefied sealant from overflowing into the port or into adjacent regions of the interior cavity.

Molded package structure with glue bleed stopper for sealing a MEMs device method of packaging a MEMs device

A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.

Semiconductor device having an identification mark

In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.

Testing process for semiconductor devices

In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process.

Separation of semiconductor devices from a wafer carrier

In one embodiment a method for manufacturing a semiconductor device comprises arranging a wafer on a carrier, the wafer comprising singulated chips; bonding the singulated chips to a support wafer, and removing the carrier.

Method of manufacturing a semiconductor device

Growing community of inventors

Munich, Germany

Stefan Martens