Koninklijke Philips Corporation N.v.

Nxp B.v.

St-ericsson Sa

Stefan Marco Koch

Hans-Joachim Gelke

Axel Hertwig

Heinz-Peter Wirtz

Steffen Gappisch

Adrian Messmer

Alexander M Jooss

Hans Joachim Gelke

Anton Reding

The present invention relates to a mobile apparatus comprising an integrated circuit to operate predefined functions, which integrated circuit is susceptible to be set in a standby operating mode wherein which said circuit can resume operation within a predefined delay. The circuit comprises configuration sequential logic having defined states that need to be stored before the circuit enters in standby mode. The mobile apparatus further comprises a power down unit for storing the states of the configuration sequential logic into a low leakage storage area during standby mode that reduces standby current considerably.

Method apparatus comprising integrated circuit and method of powering down such circuit

A portable object connectable package for an electronic device comprises: semiconductor die package, having a top surface and an opposite bottom surface, and a connector body mechanically supported by the semiconductor die package. The bottom surface includes a plurality of connection elements for connecting to a printed circuit board. The connector body includes a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO having a contacting area. The portable object connectable package is arranged to be coupled to a portable object positioner for removably positioning the contacting area of the portable object in contact with the plurality of resilient electrical connecting elements when the portable object is present in the portable object positioner.

Portable object connectable package

The data processing device according to the invention comprises a first processing unit () linked to a first bus (), a second processing unit () linked to a second bus (), a first bus master () linked to the first bus (), a second bus master () linked to the second bus (), a first and a second communication channel () linking the first and the second bus master () with each other, and a control unit () controlling the data transfer between the first and the second bus master () via the first and the second communication channel ().

Data processing device and method for transferring data

A system () comprising at least two integrated processors (Pand P). These two processors (Pand P) are operably connected via a communication channel () for exchanging information. One processor (P) has a processor bus (), a shareable unit (), and a DMA unit () with an external DMA channel (). The DMA unit () and the sharable unit () are connected to the processor bus (). The other processor (P) has an access unit () which is a connectable to the external DMA channel () of the DMA unit (). Due to this arrangement, a communication channel () can be established from the access unit () which is connectable to the external DMA channel (), the DMA unit (), and the processor bus ().

Inter-processor communication system for communication between processors

System (), e.g. a System on a chip (SoC), comprising a system bus (), a high-speed functional block () operably linked to the system bus (), and a high-speed clock line () for applying a high-speed clock to the high-speed functional block (). The system () further comprises a peripheral bus (), a low-speed functional block () operably linked to this peripheral bus (), a circuitry () for generating a wait signal (PWAIT), a low-speed clock line () for applying a low-speed clock (PCLK) to the low-speed functional block (), a select line () for feeding a select signal (PSEL) from the peripheral bus () to the low-speed functional block (), an enable line () for applying a clock enable signal (PCLKEN) to the circuitry (), and a wait line () for feeding the wait signal (PWAIT) to the high-speed functional block (). The circuitry () generates the wait signal (PWAIT) from the select line signal (PSEL) and the clock enable signal (PCLKEN).

Extension for the advanced microcontroller bus architecture (AMBA)

This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile, so-called flash memory into an ICs. Such a flash memory may be integrated by providing a dedicated flash bus which operationally links the flash memory with one or more microprocessors on the IC. Unfortunately, flash memories have relatively long access times compared to usual modern microprocessors. To achieve that the flash memory keeps pace with the microprocessor(s), a dedicated flash bus ( ) links the flash memory ( ) to the microprocessor ( ), said flash bus ( ) having a width m which is greater than the width n of the microprocessor's data bus ( ). Preferably, width m is a multiple of width n. A plurality of intermediate storage registers ( ) connects the flash bus ( ) with the data bus ( ) of the microprocessor ( ) for performing the width conversion. These intermediate storage registers ( ), together with an additional tag register ( ), may serve as cache for the microprocessor's data requests, further increasing the potential speed of the IC.

Integrated circuit with flash memory including dedicated flash bus and flash bridge

This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory ( ) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus ( ) which operationally links the flash memory ( ) with one or more microprocessors ( ) on the IC. Preferably, the flash bus ( ) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor ( ) and/or the flash memory ( ) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory ( ) and to link the flash bus via bridges ( ) to the microprocessor/s ( ,) and through a shell ( ) to the flash memory ( ). For operating such a system, a flash bus arbiter ( ) may be necessary or advantageous.

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Zurich, Switzerland

Stefan Marco Koch