Infineon Technologies Ag

Stefan Macheiner

Markus Dinkel

Thomas Stoek

Andreas Peter Meiser

Dirk Ahlers

Chau Fatt Chiang

Wae Chet Yong

Khay Chwan Saw

Thorsten Scharf

Teck Sim Lee

Swee Kah Lee

Juergen Schaefer

Chee Yang Ng

Steffen Thiele

Peter Ossimitz

Chooi Mei Chong

Lee Shuang Wang

Wolfgang Hetzel

Josef Maerz

Liu Chen

Chan Lam Cha

Amirul Afiq Hud

Jens Oetjen

Nurfarena Othman

Hock Siang Chua

Joseph Victor Soosai Prakasam

Hong Hock Tay

Wei Hing Tan

A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.

Molded semiconductor package having a negative standoff

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Chip to chip interconnect in encapsulant of molded semiconductor package

A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Lead frame-based semiconductor package

A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

Leadframe leads having fully plated end faces

A package includes a semiconductor die having a first load terminal at a first side and a second load terminal at a second side opposite the first side, a metal block attached to the second load terminal and providing a single primary thermal conduction path of the package, a first metal lead electrically connected to the first load terminal, a second metal lead electrically connected to the second load terminal, and a mold compound embedding the semiconductor die, the metal block, and each metal lead. Each metal lead and the metal block are exposed from the mold compound at a first side of the package. Each metal lead is exposed from the mold compound at a second side of the package opposite the first side, so that the package is configured for surface mounting at either the first side or the second side of the package.

Semiconductor package with top or bottom side cooling and method for manufacturing the semiconductor package

A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.

Semiconductor package having leads with a negative standoff

A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.

Semiconductor package having a filled conductive cavity

In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.

Semiconductor package for multiphase circuitry device

A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer.

Enhanced solder pad

An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

Overmolded substrate-chip arrangement with heat sink

A semiconductor arrangement includes a first and second controllable vertical n-channel semiconductor chip. Each of the controllable vertical n-channel semiconductor chips has a front side, a rear side opposite the front side, a front side main contact arranged on the front side, a rear side main contact arranged on the rear side, and a gate contact arranged on the front side for controlling an electric current between the front side main contact and the rear side main contact. The rear side contacts of the first and second semiconductor chips are electrically connected to one another.

Semiconductor arrangement

According to one embodiment, a die package is provided comprising a first die structure with a first plurality of switching elements wherein controlled current input terminals of the first plurality of switching elements are electrically coupled by a common contact region and wherein controlled current output terminals of the first plurality of switching elements are insulated from each other; a second die structure with a second plurality of switching elements wherein controlled current output terminals of the second plurality of switching elements are coupled by a common contact region and wherein controlled current input terminals of the second plurality of switching elements are insulated from each other; and wherein, for each of the first plurality of switching elements, the output terminal of the switching element is coupled with the input terminal of at least one switching element of the second plurality of switching elements.

Growing community of inventors

Kissing, Germany

Stefan Macheiner