Ferroelectric Memory Gmbh

Namlab Ggmbh

Stefan Müller

Johannes Ocker

Marko Noack

Rolf Jähne

Patrick Polakowski

Uwe Schröder

Stefano Sivero

Rashid Iqbal

Ekaterina Yurchuk

Haidi Zhou

According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Memory cell, capacitive memory structure, and methods thereof

Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

Memory cell, memory cell arrangement, and methods thereof

According to various aspects, a memory cell arrangement is provided, the memory cell arrangement including a control circuit configured to carry out a de-trapping writing scheme to write at least one memory cell of the memory cell arrangement into a memory state, the de-trapping writing scheme including providing one or more write voltage pulses and one or more de-trapping voltage pulses at the at least one memory cell, wherein the one or more de-trapping voltage pulses have opposite polarity with respect to the one or more write voltage pulses, and wherein one or more properties of the one or more write voltage pulses and of the one or more de-trapping voltage pulses are varied as long as the memory cell is not in the memory state.

Memory cell arrangement and methods thereof

A memory cell arrangement is provided that may include: a plurality of memory cells including one or more memory cells to be read out and one or more memory cells not to be read out; a control circuit defining a base voltage and configured to: apply a select voltage, a first readout voltage and a second readout voltage, to one word-line and to a source/bit-line pair corresponding to the one or more memory cells to be read out, respectively; apply a voltage that is substantially the base voltage to one or more word-lines corresponding to the one or more memory cells not to be read out; wherein both the first readout voltage and the second readout voltage are provided with an offset to the base voltage, and wherein the first readout voltage and the second readout voltage are different from one another.

A memory cell arrangement is provided that may include: a control circuit configured to supply a precondition signal and one of at least two write signals to a memory cell of the memory cell arrangement, the memory cell including a field-effect transistor structure and a remanent-polarizable layer, wherein the precondition signal is configured to bring the memory cell from an actual condition into a predefined condition, wherein the predefined condition is associated with a predefined threshold voltage of the field-effect transistor structure of the memory cell, and wherein the at least two write signals are configured to write the memory cell selectively into a first memory state or into a second memory state.

A memory cell is provided that may include: a field-effect transistor structure including a channel and a gate structure disposed adjacent to the channel, the gate structure including: one or more remanent-polarizable layers, a gate electrode, wherein the one or more remanent-polarizable layers are disposed between the gate electrode and the channel, and one or more charge storage structures disposed between at least one of the one or more remanent-polarizable layers and the channel and/or the one or more remanent-polarizable layers and the gate electrode, the one or more charge storage structures are configured to stabilize a polarization state associated with the one or more remanent-polarizable layers by trapping charge in the one or more charge storage structures.

Memory cell, memory cell arrangement and methods thereof

An integrated circuit comprises a ferroelectric memory cell comprising a ferroelectric film comprising a binary oxide ferroelectric with the formula XOwhere X represents a transition metal. The ferroelectric film is a polycrystalline film having a plurality of crystal grains, wherein the crystal grains are oriented along a predetermined crystal axis, or the ferroelectric film is a monocrystalline film, wherein the ferroelectric film comprises additives promoting formation of the crystal structure of the monocrystalline film and/or wherein the memory cell comprises a crystallinity-promoting layer that is directly in contact with the ferroelectric film and promotes formation of the crystal structure of the monocrystalline film.

Integrated circuit including a ferroelectric memory cell and manufacturing method thereof

According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Memory cell and methods thereof

According to various embodiments, a memory cell may include: a channel region, a gate isolation structure disposed at the channel region; and a memory structure disposed over the gate isolation structure, the memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure, the gate isolation structure, and the channel region form a first capacitor structure defining a capacitor area of a first size; and wherein the first electrode structure, the at least one remanent-polarizable layer, and the second electrode structure form a second capacitor structure defining a capacitor area of a second size, wherein the second size is less than the first size.

A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

Charge storage ferroelectric memory hybrid and erase scheme

An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a ferroelectric material that is at least partially in a ferroelectric state and further includes, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr).

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Dresden, Germany

Stefan Müller