Infineon Technologies Ag

Lantiq Deutschland Gmbh

Infineon Technologies LLC

Stefan Linz

Helmut Reinig

Christian Klein

A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Selectable access rates in a memory and memory communication system

In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Method for measuring a delay time of a digital circuit and corresponding device and digital circuit

In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being allocated a supply voltage. The hardware description code is transformed into a net list that contains logical cells and their connections. A specific supply voltage is assigned to each cell by a unique identifier. Afterward, a time sequence analysis of the circuit is performed taking account of the identifiers of the cells.

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Stefan Linz