Commissariat a L'energie Atomique Et Aux Energies Alternatives

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Commissariat a L'energie Atomique

Centre National De La Recherche Scientifique

Stefan Landis

Nicolas Posseme

Lamia Nouri

Vincent Reboud

Hubert Teyssedre

Sergio Nicoletti

Sebastien Barnola

Frederic-Xavier Gaillard

Carole Pernel

Thibaut David

Michael May

Etienne Rognin

Laurent Mollard

Raluca Tiron

Florian Pebay-Peyroula

Aziz Zenasni

Alexandre Mary

Frédéric-Xavier Gaillard

Valentina Ivanova-Hristova

Sébastien Barnola

Luc Andre

Sebastien Pauliac

Cecile Gourgon

Johann Coraux

Jean-Herve Tortai

Ujwol Palanchoke

Nicolas Chaix

Michaël May

Sébastien Berard-Bergery

Fr D Ric-Xavier Gaillard

Sébastien Pauliac

A multispectral filter matrix for an electromagnetic wave, the matrix including at least a first and a second optoelectronic element, each optoelectronic element including a colour filter and a photoelectric transducer facing the filter, each colour filter forming a Fabry-Perot cavity including a first reflective layer, a second reflective layer and a Fabry-Perot cavity layer of dielectric material between the first reflective layer and the second reflective layer, the layer of dielectric material including a lower surface, in contact with the first reflective layer; the lower surface being curved, an upper surface in contact with the second reflective layer, the upper surface being curved, the average thicknesses of the two layers of dielectric material of the two filters being different.

Multispectral filter matrix with curved Fabry-Perot filters and methods for manufacturing the same

A method for manufacturing a mould for nanoprinting and the associated mould, includes providing a substrate having a layer, and at least one ion implantation configured so as to obtain in the layer, at least one first non-implanted portion or portion having a first implantation, at least one second portion having a second implantation, and a third non-implanted portion distinct from the first portion. After implantation, the method includes etching the layer configured so as to have a different etching speed between at least the second portion and the third portion, so as to etch through the openings of an etching mask, a plurality of patterns of different heights being included in the layer.

Method for manufacturing a mould for nanoprinting and associated mould

The invention relates to a method for making an individualization zone of a microchip comprising a first (A) and a second (A) level of electrical tracks (), and a conductor layer (A) comprising via holes (), the method comprising the following steps:

Method of making an individualization zone of an integrated circuit

A method for making an individualization zone of a microchip comprising a first level and a second level of electrical tracks, and a level of interconnections comprising vias. The method includes: providing the first level and a dielectric layer, making a hard metal mask on the dielectric layer, etching the dielectric layer through the mask openings by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask by hydrolysis so as to form randomly distributed residues at certain openings, and filling the openings so as to form at least the vias of the level of interconnections, the vias comprising functional vias at the openings without residues and inactive vias at the openings with residues.

A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.

Process of realization on a plate of a plurality of chips, each with an individualization area

A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

Formation of reliefs on the surface of a substrate

A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.

Method of manufacturing a microelectronic device having an array of inclined reliefs

A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.

Process of realization of an area of individualization of an integrated circuit

A method for functionalising a substrate intended for the self-assembly of a block copolymer, includes depositing on the surface of a substrate a layer of a first polymer material, the first polymer having a first chemical affinity with respect to the block copolymer; grafting one part only of the first polymer material layer onto the surface of the substrate; printing, using a mould, patterns in a sacrificial layer arranged above the grafted part of the first polymer material layer; transferring the patterns of the sacrificial layer into the grafted part of the first polymer material layer, until the substrate is reached; and removing at least one part of the sacrificial layer by wet etching, so as to uncover the grafted part of the first polymer material layer.

Method for functionalising a substrate

A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity &#x3c1;1 less than a resistivity &#x3c1;2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.

Method for producing patterns in a substrate

The invention relates to a method of securing an integrated circuit during its fabrication on a wafer, said method including the following steps:

Method for securing an integrated circuit during fabrication

A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.

Customisation of an integrated circuit during the realisation thereof

A method for determining at least one reflow parameter for obtaining a structure approximating a sought structure by reflowing an initial structure different to the sought structure, the initial structure including at least one pattern formed in a thermo-deformable layer arranged on a substrate. The thermo-deformable layer forms a residual layer surrounding each pattern and from which each pattern extends such that each pattern has an interface only with the surrounding medium. The method includes: predicting progression over time of geometry of the initial structure subject to reflow, to obtain a plurality of predicted structures each associated with reflow parameters including at least a reflow time and a reflow temperature; computing correlation values of the geometry of each predicted structure with respect to the sought structure; identifying reflow parameters for obtaining the predicted structure offering a highest correlation value.

Method for obtaining at least one structure approximating a sought structure by reflow

The invention relates in particular to a method for producing subsequent patterns in an underlying layer (), the method comprising at least one step of producing prior patterns in a carbon imprintable layer () on top of the underlying layer (), the production of the prior patterns involving nanoimprinting of the imprintable layer () and leave in place a continuous layer formed by the imprintable layer () and covering the underlying layer (), characterized in that it comprises the following step: at least one step of modifying the underlying layer () via ion implantation () in the underlying layer (), the implantation () being carried out through the imprintable layer () comprising the subsequent patterns, the parameters of the implantation () being chosen in such a way as to form, in the underlying layer (), implanted zones () and non-implanted zones, the non-implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns.

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Tullins, France

Stefan Landis