Infineon Technologies Ag

International Business Machines Corporation

Siemens Aktiengesellschaft

Stefan Lammers

Dietmar Gogl

Thomas B&ouml;hm

Hans-Heinrich Viehmann

Helmut Kandolf

Zoltan Manyoki

Heinz H&ouml;nigschmid

Martin Freitag

John Kenneth DeBrosse

Georg Braun

Werner Weber

Helmut Fischer

Heinz Hoenigschmid

Thomas M Maffitt

Thomas Roehr

Christian Arndt

Thomas Röhr

Robert Esterl

Hans Viehmann

Gerhard M&uuml;ller

Thomas Böhm

John E Barwin

A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Method and apparatus for current sense amplifier calibration in MRAM devices

A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

Semiconductor memory device having a plurality of memory areas with memory elements

The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.

Precharging the write path of an MRAM device for fast write operation

A reference current distribution method and structure thereof for MRAM devices. An MRAM array includes current reference paths with substantially uniform length and resistance for all current paths flowing from the global reference current generator (GRCG) to a plurality of local current generators (LCGs), each LCG being coupled to at least one sub-array. The conductive wire segments that couple the LCGs to the GRCG are positioned such that all reference current path lengths from the GRCG to each LCG are substantially the same, ensuring that the resistance of all reference current paths is substantially the same and the amount of reference current provided by the GRCG to the LCGs is substantially the same. An advantage of an embodiment of present invention may be that the write margin is increased for the MRAM chip.

Reference current distribution in MRAM devices

A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.

Cross-point MRAM array with reduced voltage drop across MTJ's

An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter) and a pair of latches (for example, latchesand). One latch has as its input an input signal to be converted and the other latch has as its input an inverse of the input signal. The latches maybe clocked by a differential mode clock and remove a timing mismatch between the input signal and its inverse that is incurred via the inverter. The latch outputs are then provided to a differential mode buffer to perform signal voltage and current compatibility transformations.

Circuit for transforming a single ended signal into a differential mode signal

An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example, control circuit) coupled to a dual function OCD/ODT circuit (for example, OCD/ODT circuit) with an enable line coupled to the control circuit. The control circuit may be used to selectively choose OCD and ODT functionality based on a value on the enable line. With the control circuit choosing OCD, the dual function OCD/ODT circuit functions as an OCD circuit, placing signals provided through the control circuit onto a transmission line. With the control circuit choosing ODT, the dual function OCD/ODT circuit becomes terminating resistors for incoming signals on a transmission line. The use of a single circuit for both OCD and ODT functions can save both integrated circuit real-estate and implementation costs due to a reduction in use of circuit elements.

CML (current mode logic) OCD (off chip driver)&#x2014;ODT (on die termination) circuit for bidirectional data transmission

An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer ) in both buffered (via a buffer (for example, buffer )) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.

Current mode logic (CML) circuit concept for a variable delay element

An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter ) and an output transistor (for example, output transistor ) that when the single ended converter is in standby may pull the output of the single ended converter to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.

Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption

A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

Magnetic memory configuration

The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.

MRAM semiconductor memory configuration with redundant cell arrays

The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

Magnetoresistive memory (MRAM)

An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

Integrated memory with memory cell array

A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V and a voltage V <V are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V V )/2 and to have a maximum cell voltage of &plusmn;(V &minus;V )/2.

Configuration and method for the low-loss writing of an MRAM

A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.

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South Burlington, VT, United States of America

Stefan Lammers