Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec Vzw

Samsung Electronics Co., Ltd.

Imec

Stefan Kubicek

Ruoyu Li

Shou-Zen Chang

Hag-Ju Cho

Anabela Veloso

Bogdan Govoreanu

HongYu Yu

Fahd Ayyalil Mohiyaddin

George Eduard Simion

Yasutoshi Okuno

Boon Teik Chan

Lars-Ake Ragnarsson

Tom Schram

Naohisa Sengoku

Steven Brebels

Joshua Tseng

Florin Ciubotaru

Julien Jussot

Thomas Y Hoffman

Clement Godfrin

A qubit device includes first and second linear qubit arrays. Each qubit array includes a semiconductor substrate, control gates configured to define a single row of quantum dots along the substrate, and nanomagnets distributed along the row of quantum dots such that a nanomagnet is arranged at every other pair of quantum dots of the row of quantum dots. Each nanomagnet has an out-of-plane magnetization with respect to the substrate, where the rows of the first and second arrays extend in a common row direction and are separated along a direction transverse to the row direction. The qubit device further includes superconducting resonators connecting pairs of quantum dots between the first and second arrays. Each pair of quantum dots in the first array is configured to couple with a superconducting resonator of the first set to connect with a different pair of quantum dots of the second array.

Qubit device

According to an aspect of the present inventive concept there is provided a qubit device comprising: a semiconductor substrate layer; a set of control gates configured to define a row of electrostatically confined quantum dots along the substrate layer, each quantum dot being suitable for holding a qubit; and a set of nanomagnets arranged in a row over the substrate layer such that a nanomagnet is arranged above every other quantum dot of the row of quantum dots, wherein each nanomagnet has an out-of-plane magnetization with respect to the substrate layer and wherein every other quantum dot is subjected to an out-of-plane magnetic field generated by a respective nanomagnet, such that a qubit spin resonance frequency of every other quantum dot is shifted with respect to an adjacent quantum dot of the row of quantum dots.

Qubit device and a method for operating a qubit device

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

Method for processing a semiconductor device with two closely spaced gates

A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.

Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereof

A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Semiconductor device and method for fabricating the same

Growing community of inventors

Pellenberg, Belgium

Stefan Kubicek