Infineon Technologies Ag

Infineon Technologies Austria Ag

Stefan Kramp

Stefan Woehlert

Stefan Krivec

Ronny Kern

Gregor Langer

Hannes Winkler

Klaus Schiess

Oliver Haeberlen

Jens Peter Konrath

Romain Esteve

Wolfgang Bergner

Ravi Keshav Joshi

Andreas Voerckel

Erwin Thalmann

Jochen Hilsenbeck

Florian Grasse

Michael Leutschacher

Marco Koitz

Richard Gaisberger

Christian Musshoff

Hiroshi Narahashi

Grzegorz Lupina

Ralf Siemieniec

Oliver Blank

Mario Kleindienst

A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.

Chip with a silicon carbide substrate

A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

Semiconductor device and method for forming a semiconductor device

A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

Process for producing an electrical contact on a silicon carbide substrate

A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

Electrical contact connection on silicon carbide substrate

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.

Semiconductor chip and method for forming a chip pad

A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Method of manufacturing a semiconductor device

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.

A method for testing semiconductor dies includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a first semiconductor die of the plurality of semiconductor dies by electrically connecting the test apparatus with the first contact element of the first semiconductor die and the contact location.

Method for testing semiconductor dies

A semiconductor device includes compensation structures that extend from a first surface into a semiconductor portion. Sections of the semiconductor portion between neighboring ones of the compensation structures form semiconductor mesas. A field dielectric separating a field electrode in the compensation structures from the semiconductor portion includes a thermally grown portion, which directly adjoins the semiconductor portion. A not fully densified deposited portion of the field dielectric has a lower density than the thermally grown portion.

Semiconductor device and trench field plate field effect transistor with a field dielectric including thermally grown and deposited portions

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.

Semiconductor device and a method for manufacturing a semiconductor device

A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location.

Method for testing semiconductor dies and a test apparatus

A semiconductor device and method of manufacturing a semiconductor device. One embodiment provides an electrically conductive carrier. A semiconductor chip is placed over the carrier. An electrically insulating layer is applied over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. A first through-hole is in the electrically insulating layer. Solder material is deposited in the first through-hole and on the second face of the electrically insulating layer.

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Villach, Austria

Stefan Kramp