Texas Instruments Corporation

Interuniversitair Microelektronica Centrum (Imec)

Inter-University Microelectronics Center (Imec)

Stefan Janssens

Francky Catthoor

Hugo De Man

Miguel Miranda

Bhanu Kapoor

Lode Jm Nachtergaele

A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally executes a sequence of a plurality of pre-customized routines, usually for which it has been optimized. To provide some flexibility for design changes and optimizations, a controller for monitoring the customized processor during execution of routines is provided to select one of a set of pre-customized processing interruption points and for switching context from the customized processor to the flexible processor at the interruption point. The customized processor can then be switched off and the flexible processor carries out a modified routine. By using sharable a data store, the context switch can be chosen at a time when all relevant data is in the sharable data store. This means that the flexible processor can pick up the modified processing cleanly. After the modified processing the flexible processor writes back new data into the data store and the customized processor can continue processing either where it left off or may skip a certain number of cycles as instructed by the flexible processor, before beginning processing of the new data.

Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors

A battery-powered computing system (20) including video decoding capability, particularly as pertinent to the H.263 standard, is disclosed. The system (20) includes a main integrated circuit (30) having an on-chip central processing unit (CPU) (32) and on-chip shared memory (33) for the temporary buffering of video image data that is retrieved and generated during the video decoding process. The CPU (32) is programmed to perform a combined P and B prediction process (46) upon a previously predicted P frame (P.sub.T-1), with accesses to internal buffers in shared memory (33) instead of to main memory (40). Preferably, inverse transform processes (48, 52) also access shared memory (33) rather than main memory (40). The combined P and B prediction process (46) preferably handles unrestricted motion vectors using edge pixels (P.sub.edge) stored in an edge buffer (44e) in the on-chip memory (33), by modifying (58, 60) motion vector components (MVx, MVy) that point outside of the displayable video image, and retrieving the corresponding edge pixels (P.sub.edge) from the edge buffer (44e) in this event. The on-chip memory (33) preferably also includes a buffer (NEWBFR) for storing current predicted P blocks, such that the previous predicted P frame (P.sub.T-1) and the current predicted P frame (P.sub.T) can share the same memory space (old/newframe). The power requirements of the video decoding process are thus much reduced, as memory accesses to large, off-chip, main memory (40) are limited.

Low power video decoder system with block-based motion compensation

Growing community of inventors

Lennik, Belgium

Stefan Janssens