Infineon Technologies Ag

Qimonda Ag

Imec

Stefan Jakschik

Thomas Hecht

Uwe Schröder

Matthias Goldbach

Stephan Kudelka

Harald Seidl

Martin Gutsche

Uwe Schroeder

Albert Birner

Nadine Collaert

Peter Baars

Marcus Johannes Henricus Van Dal

Wolfgang Roesner

Hans-Peter Moll

Gerhard Enders

Thomas Mikolajick

Martin Popp

Klaus Muemmler

Peter Moll

Till Schlösser

Jorge Adrian Kittl

Werner Graf

Peter Lahnor

Lars Heineck

Ulrich Mantz

Bernd Hintze

Annette Saenger

Björn Fischer

Odo Wunnicke

Arnd Scholz

Tim Boescke

Andreas Orth

Johannes Heitmann

Anne Lauwers

Matthias Schmeide

Andrei Josiek

Alejandro Avellan

Gouri Sankar Kar

A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.

Multi-gate semiconductor devices with improved carrier mobility

The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.

Electrode of an integrated circuit

One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Interconnect structure for semiconductor devices

A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction semiconductor device thus obtained are disclosed. In one aspect, the method comprises forming a blocking region for preventing diffusion of metal from the metal-semiconductor compound of the first control electrode to the metal-semiconductor compound of the second control electrode, the blocking region being formed at a location where an interface between the first and second control electrodes is to be formed or is formed. By preventing metal to diffuse from the one to the other control electrode the constitution of the metal-semiconductor compounds of the first and second control electrodes may remain substantially unchanged during e.g. thermal steps in further processing of the device.

Dual workfunction semiconductor device

A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.

Gate electrode structure, MOS field effect transistors and methods of manufacturing the same

A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

Method of fabricating multi-gate semiconductor devices with improved carrier mobility

An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric () and at least one connection electrode () are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric () or the connection electrode () are formed in such a manner that transient polarization effects are prevented or at least reduced.

Method for fabricating an electrical component

A method produces stacked capacitors for dynamic memory cells, in which a number of trenches () are formed in the masking layer (), each trench () being arranged above a respective contact plug () and extending from the top () of the masking layer () to the contact plugs (). A conductive layer () covers the side walls () of the trenches () and the contact plugs () in order to form a first electrode () of a stacked capacitor (). In an upper region (), which is remote from the contact stack (), the conductive layer () is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Stacked capacitor and method for producing stacked capacitors for dynamic memory cells

The present invention provides a coating process for patterned substrate surfaces, in which a substrate () is provided, the substrate having a surface () which is patterned in a substrate patterning region () and has one or more trenches () that are to be filled to a predetermined filling height (), a catalyst layer () is introduced into the trenches () that are to be filled, a reaction layer () is deposited catalytically in the trenches () that are to be filled, the catalytically deposited reaction layer () is densified in the trenches () that are to be filled, and the introduction of the catalyst layer () and the catalytic deposition of the reaction layer () are repeated until the trenches () that are to be filled have been filled to the predetermined filling height ().

Coating process for patterned substrate surfaces

The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.

Method for determining the depth of a buried structure

A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

Method for fabricating microchips using metal oxide masks

A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material

A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices

Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

Charge-trapping memory device and method of production

A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

Growing community of inventors

Dresden, Germany

Stefan Jakschik