Infineon Technologies Ag

Stefan Gruss

Hans-Georg Froehlich

Mirko Vogt

Rainer Pforr

Werner Graf

Oliver Genz

Kristin Schupke

Lars Heineck

Mario Hennig

Lothar Bauch

Momtchil Stavrev

Alexander Reb

Hans-Georg Fröhlich

Detlef Hofmann

Percy Heger

Ansgar Teipel

Matthias Handke

Antje Laessig

Guido Thielscher

A method for reducing an overlay error of structures of a layer to be patterned relative to those of a reference layer includes formation of standard measurement marks assigned to one another in the two layers for determining an overlay error and for setting up further measurement marks for determining an additional optical imaging error of the projection system at least in the current layer. The further measurement marks have a geometry adapted to the geometry of selected structures of the circuit patterns to be transferred by projection from masks onto semiconductor substrates. An imaging error affects circuit structures and further measurement marks in the same way. An alignment correction for a subsequent exposure can be calculated from the measured positional deviations between the two standard measurement marks and between the standard measurement mark and the further measurement mark of the layer currently to be patterned.

Method for reducing an overlay error and measurement mark for carrying out the same

A method, suitable to photolithographie projection, for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure into at least one resist layer above the substrate, wherein the first test structure includes a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.

Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer

Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Method for fabricating a contact hole plane in a memory module

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Dresden, Germany

Stefan Gruss