Nxp B.v.

Koninklijke Philips Corporation N.V.

Stefan Gerhard Erich Butselaar

Cecilius Gerardus Kwakernaat

Hendrik Boezen

Cornelis Klaas Waardenburg

Jelle Nico Wolthek

Harm Gerwin Joan Voss

Clemens Gerhardus Johannes De Haas

Patrick Willem Hubert Heuts

Ben Gelissen

Louk Boomkamp

Mehdi El-Ghorba

Cornelis Klass Waardenburg

An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

Interference-tolerant communication circuit

The invention relates to a receiver for a differential data bus with two resistive branches (), with a differential amplifier with two transistors (), with a resistor (), and with a control logic () that controls a switch () with which a current from a current source () is switchable to either side of the resistor (), which resistor couples the two transistors (), and with two operational amplifiers () which are coupled to the two transistors () of the differential amplifier with opposite poles, in which receiver the control logic detects from the output signals of the two operational amplifiers () whether a '0' or a '1' is expected on the bus and which receiver sets the switch () accordingly so that a comparison with the received bus signal is made.

Apparatus for receiving differential signal using a differential amplifier

The invention relates to a receiver for a differential bus with a switch control logic (), with two branches with resistive elements (and) and with switches () for switching the resistive elements, in which the switch control logic sets the switches&#x2014;in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,&#x2014;and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device. The receiver therefore provides good balancing and common mode rejection.

Receiver for a differential data bus

The communication bus system comprises a plurality of node circuits (-) and a relay circuit () coupling the node circuits (-). The relay circuit () has a transceiver circuit () for relaying messages () between the node circuits (-) in a normal mode. The transceiver circuit () is powered down in a sleep mode. A detector circuit () detects an incoming message () when the relay circuit () is in a sleep mode. A mode control circuit () powers up the transceiver () in response to detection of an incoming message (). Steps are taken that ensure, in the normal mode, that messages () will not be relayed in unreadable form. The mode control circuit () is arranged to cause the transceiver () to relay a remainder () of the incoming message () after power up. In an embodiment the power needed to transmit the remainder () of the message () is drained from a capacitor () in the power supply () before the power supply () controls the power supply voltage in the normal mode. In another embodiment the detector circuit () temporarily controls the direction of operation of the transceivers () at the start of the normal mode instead of further detectors (-) that normally control the direction of operation in the normal mode.

Communication bus system operable in a sleep mode and a normal mode

An integrated circuit has an input connection for connecting an external signal conductor that passes signals to execute functions in the device. The external signal conductor can pick up strong interfering signals with high frequency content, for example when the device is used in a car. To protect against unintended execution of functions the device contains a timer circuit comprising a capacitance and a current supplying circuit coupled to an integration node. A discharge diode is coupled between the input connection and the integration node, with a polarity such that the discharge diode, when in forward bias, is capable of draining current from the current supplying circuit. A detector is coupled to the integration node for generating a signal to be supplied to the integrated circuit device to respond to a signal transition on the conductor. The diode serves to reset integration on the integration node before the detector detects the transition in case of short pulses. By using a diode instead of a switching transistor the circuit is more robust against the effect of interfering pulses.

Transition detection at input of integrated circuit device

In a network a star node (SN) interconnects a plurality of stations (ST&#x2013;ST). The star node (SN) has interfaces (I&#x2013;I), each having a connection terminal (BP) for connecting a selected one of the stations to the star node (SN) and each interface receives at a connection terminal (BP) a signal from the station associated with that interface and forwards the received signal to the connection terminal (BP) of the other interfaces. The star node (SN) further has a common terminal (RT) and each interface has a receiver (CMP) coupled to the connection terminal (BP) for receiving the signal from the associated station, a transmitter (TR) coupled to the connection terminal (BP), a first activity detector (A) for generating a first activity signal (AS) in response to signal transitions at an input (CIP) of the receiver (CMP), a second activity detector (A) for generating a second activity signal (AS) in response to signal transitions at the common terminal (RT), a first switch (SW) for disabling signal transfer from the receiver (CMP) to the common terminal (RT) in response to the second activity signal (AS), and a second switch (SW) for disabling signal transfer from the common terminal (RT) to the transmitter (TR) in response to the first activity signal (AS). The structure of the interface allows easy expansion of the number of interfaces within the star node (SN) and a data protocol without a preamble.

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Nijmegen, Netherlands

Stefan Gerhard Erich Butselaar