Nxp Usa, Inc.

Nxp B.v.

Freescale Semiconductor,inc.

Stefan Doll

Michael Rohleder

Markus Regner

Rohit Kumar Sinha

Sandeep Jain

Garima Sharda

Amol Agarwal

Andreas Lentz

Vandana Sapra

Clemens Alfred Roettgermann

Hubert Martin Bode

Thomas Henry Luedeke

Vivek Mohan Sharma

Neha Srivastava

Anurag Jindal

Nikila Krishnamoorthy

Timothy J Strauss

Rolf Dieter Schlagenhaft

Joel Ray Knight

Hubert Glenn Carson, Jr

Peter Limmer

Adrian Lee Carleton

Kamel Musa Khalaf

Hilario Manuel Garza

Jürgen W Frank

Nitin Moudgil

Ankur Krishna

Arnavesh Varun Giri

Dhruv Satsangi

A System-on-Chip (SoC) includes first and second voltage supply pins configured to receive first and second supply voltages, respectively, a first supply path beginning at the first supply pin, and a supply proportion checker. The first supply path includes a first plurality of voltage supply nodes and a supply switch coupled between adjacent voltage supply nodes, wherein each node is configured to provide a corresponding internal voltage supply to a corresponding portion of the SoC. The supply proportion checker is coupled to receive the corresponding internal voltage supply from each voltage supply node, and configured to determine whether a first internal voltage supply supplied by a first supply node of the first plurality of nodes has a legitimate proportion to a second internal voltage supply supplied by a second supply node of the first plurality of nodes, wherein the legitimacy is checked using only resistors which do not require trimming.

Supply voltage proportionality monitoring in a system-on-chip (SOC)

A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.

Glitch detector

A system for securing a secret word during a read of the secret word from a read-only memory (ROM) is disclosed. The system includes a memory controller coupled to the ROM and a random number generator coupled to the memory controller. The random number generator is configured to generate a random number. The system further includes a number shuffler coupled to the random number generator and the memory controller. The number shuffler is configured to generate a bit read order based on the random number and the memory controller is configured to read bits of the secret word from the ROM according to the bit read order.

Side channel attack protection

A fully digital integrated circuit apparatus () and method () are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit () connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit () connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry () for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Method and apparatus for digital only secure test mode entry

A clock glitch alerting circuit is configured to detect a glitch in an input clock signal, and activate and provide an alert signal to a security controller when the glitch is detected. The clock glitch alerting circuit is further configured to delay the input clock signal based on multiple selection signals, and provide one of a delayed clock output signal and a filtered clock output signal to the security controller based on the alert signal. The clock glitch alerting circuit is further configured to generate and provide a count value to the security controller that indicates a time duration available by the security controller to execute a security critical operation after receiving the activated alert signal.

Clock glitch alerting circuit

A method, system, and apparatus are provided for preventing glitch attacks by using a glitch processing hardware unit (1) to deactivate a glitch filter connected between the monitored line and a reset processing unit in response to detecting a voltage glitch on a monitored line during a specified security system sequence and (2) to automatically drive a requested reaction in response to the voltage glitch by driving one of a plurality of configurable reactions comprising a device reset reaction and a process restart request, thereby preventing the voltage glitch from maliciously influencing the specified security system sequence.

Automatic reset filter deactivation during critical security processes

Various embodiments relate to a circuit, including: a first secure circuit configured to receive an input and to produce a first output; a first delay circuit configured to receive the first output and to produce a first delayed output delayed by a time N; a second delay circuit configured to receive the input and to produce a delayed input delayed by a time N; a second secure circuit configured to receive the delayed input and to produce a second delayed output; and a comparator configured to compare the first delayed output to the second delayed output and to produce a result, wherein the result is one of the first delayed output or second delayed output when the first delayed output matches the second delayed output and the result is an error value when the first delayed output does not match the second delayed output.

Fault attack protection against synchronized fault injections

An integrated circuit includes a security module with multiple stages arranged in a pipeline, with each stage executing a different operation for accessing stored lifecycle (LC) information. For each portion of LC being accessed, each stage performs N iterations of its corresponding operation, whereby N is an integer greater than two, and crosschecks the results of successive iterations to ensure that the results of the operation are consistent. In addition, the stages of the security module are overlapping, such that different stages can perform different iterations concurrently. These concurrent operations at different stages are organized such that they may also be crosschecked and thereby confirm 'offset' results between the stages.

Integrated circuit lifecycle security with redundant and overlapping crosschecks

A bit storage device, integrated circuit, and method are provided. The bit storage device comprises registers to store an actual value, an inverse value, a differential actual value, and a differential inverse value, a validation circuit including validation inputs coupled to outputs of the registers and including a validity output to provide a validity indication, and a write circuit including write circuit inputs coupled to the registers, the write circuit configured to cause, at a first clock edge, the first register to store the actual value and either the second register to store the inverse value or the fourth register to store the differential inverse value, and, at a second clock edge, the third register to store the differential actual value and the other of the second register and the fourth register to store to store the inverse value or the differential inverse value, respectively.

Safe secure bit storage with validation

A method provides access to an integrated circuit which may comprise a storage containing an unalterable first security key and a memory containing a second security key. The method may comprise:

Integrated circuit access

An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

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Munich, Germany

Stefan Doll