Infineon Technologies Ag

Micron Technology Incorporated

Siemens Aktiengesellschaft

Qimonda Ag

Sew-eurodrive Gmbh & Co Kg

Infineon Technology Ag

Stefan Dietrich

Thomas Hein

Christian Weis

Peter Schr&ouml;gmeier

Peter Schroegmeier

Sabine Sch&ouml;niger

Sabine Kieser

Thilo Marx

Natalija Jovanovic

Martin Brox

Michael Dieter Richter

Patrick Heyne

Torsten Partsch

Michael Markert

Ronny Schneider

Peter Barton

Michael Bernhard Sommer

Pramod Acharya

Peter Schrögmeier

Rex Kho

Peter Schrogmeier

Sabine Schoniger

Wolfgang Anton Spirkl

Peter Mayer

Heinz Hoenigschmid

Markus Wöppermann

Milena Ivanov

Konstantin Völker

Musa Saglam

Anette Bunka

Werner Jung

Lothar M&uuml;ller

Daniel Metz

Renaud Becker

Josef Schmidt

Peter Gregorius

Manfred Schneegans

Paul Wallner

Matthias Hauck

Manfred Dobler

Ingo Schütterle

Luca De Ambroggi

Torsten Koker

Marek Lewandowski

Matthias Grewe

Bernd-Friedrich Scholl

Gerhard Dittes

Marco Redaelli

Armin Rettenberger

Martin Doppelbauer

Johannes Schuchart

Michael Haug

Acharya Pramod

Friedhelm Metzler

Sabine Sch&ouml;niger Kieser

Ingo Schuetterle

Birgit Haase

Mario Zucker

Alexander Hirsch

Simon Weber

Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output is transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Bit and signal level mapping

Methods, systems, and devices for data inversion techniques are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some portions of some multi-symbol signals may be inverted. A transmitting device may determine to invert one or more data symbols based on one or more parameters. A receiving device may determine that one or more data symbols are inverted and may re-invert the one or more data symbols (e.g., to an original value). When receiving or transmitting a multi-symbol signal, a device may invert or re-invert a data symbol by changing a value of one bit of the data symbol. Additionally or alternatively, a device may invert or re-invert a data symbol of a multi-symbol signal by inverting a physical level of the signal across an axis located between or associated with one or more physical levels.

Data inversion techniques

Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.

Postamble for multi-level signal modulation

Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations generate one or more bits of CRC output per symbol of an associated signal and the output are transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process is performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process is configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

Methods, systems, and devices related to error detection code generation techniques are described. A memory device may identify a first set of bits for transmission to a host device and calculate an error detection code associated with the first set of bits. Prior to transmitting the first set of bits, the memory device may modify one or more bits of the first set of bits to generate a second set of bits for transmission from the memory device to the host device. The memory device may modify one or more bits of the first error detection code to generate a second error detection code based on a parity of the modified one or more bits of the first set of bits. The memory device may transmit the second set of bits and the second error detection code to the host device.

Error detection code generation techniques

A gear unit having a shaft, particularly an input shaft, a fan impeller being joined in rotatably fixed manner to the shaft, a fan cowl, which at least partially surrounds the fan impeller, being mounted on the gear housing, a separating plate for separating the pressure chamber of the fan from the suction chamber of the fan being joined to the fan cowl, the separating plate having an air inlet for the fan impeller and being disposed on the side of the fan impeller facing away axially from the gear unit.

Gear unit having a shaft

Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.

Techniques for low power operation

A bearing system having a housing component, a shaft being supported in the housing component with the aid of a bearing, especially using a roller bearing, wherein the bearing is accommodated in a stepped bore in the housing component, which especially extends through the housing component, a lid part seals the stepped bore, especially with respect to the outside, the lid part is frictionally connected to the housing component, the lid part is accommodated in the stepped bore, a surface section of the outside of the lid part is situated in alignment with a step of the stepped bore, in particular in such a way that the surface section is situated on an axial position of the step.

Bearing system and gear unit

A gear unit having a shaft, in particular an input shaft, a fan impeller being connected to the shaft in a torsionally fixed manner, a fan hood being connected to the gear unit housing, which at least partially encloses the fan impeller, a separation plate for separating the pressure chamber of the fan from the suction chamber of the fan being connected to the fan hood, where the separation plate has an air intake opening for the fan impeller and is situated on the side of the fan impeller facing axially away from the gear unit, the fan impeller has an upper and a lower cover disk, which are axially set apart from each other, and fan blades are disposed between the cover disks, so that channels are formed, the radial clearance of the air intake opening being disposed within, especially centrally within, the radial clearance region covered by the upper cover disk, and the air intake opening is disposed axially within, especially centrally within, the axial region covered by the upper cover disk.

Gearbox with a shaft

Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.

Apparatuses and methods for high speed writing test mode for memories

A memory system includes a memory device, a command clock (CK_t clock) that provides a first clock signal at a first frequency, and a data path clock (WCK_t clock) that provides a second clock signal at a second frequency different than the first frequency. Data path circuitry is synchronized with the WCK_t clock and provides an error detection code (EDC) hold pattern during an idle state. EDC hold pattern synchronization logic synchronizes a start of transmission of the EDC hold pattern synchronous to the CK_t clock.

Error detection code hold pattern synchronization

An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.

Systems and methods for double data rate serialization in a memory system

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Türkenfeld, Germany

Stefan Dietrich