Imec

Epigan Nv

Vrije Universiteit Brussel

Katholieke Universiteit Leuven

Interuniversitair Microelektronica Centrum (imec)

Soitec Belgium

Imec Vzw

Soitec

Stefan Degroote

Joff Derluyn

Kai Cheng

Marianne Germain

Gustaaf Regina Borghs

Christelle Veytizou

Ruben Lieten

Maarten Leys

Roland Pusche

Germain Marianne

A system for in-situ measurement of a curvature of a surface of a wafer comprises: a multiwavelength light source module, adapted to emit incident light comprising a plurality of wavelengths; an optical setup configured to combine the incident light into a single beam and to guide the single beam towards a surface of a wafer such that the single beam hits the surface at a single measuring spot on the surface; and a curvature determining unit, configured to determine a curvature of the surface of the wafer from reflected light corresponding to the single beam being reflected on the surface at the single measuring spot.

Wafer surface curvature determining system

A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.

Semiconductor structure comprising an active semiconductor layer of the III-V type on a buffer layer stack and method for producing semiconductor structure

A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: &#x2014;a III-N layer; &#x2014;a AI-III-N layer on top of the III-N layer; &#x2014;a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.

Device comprising a III-N layer stack with improved passivation layer and associated manufacturing method

Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.

Method for growing III-V epitaxial layers

Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).

Method for growing III-V epitaxial layers and semiconductor structure

The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a Hflux or hydrogen originating from dissociation of GeHand/or to a non-reactive gas source such as N, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer. The present invention also provides a method for the production of a photovoltaic cell or a photo-electrolysis cell or for forming a CMOS device by using the method according to embodiments of the invention and a substrate comprising a crystalline germanium layer formed by a method according to embodiments of the invention.

Method for producing a crystalline germanium layer on a substrate

A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.

Semiconductor device and method of manufacturing thereof

An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

Method of manufacturing an integrated semiconductor substrate structure with device areas for definition of GaN-based devices and CMOS devices

The present invention relates a method for forming a monocrystalline GeN layer () on a substrate () comprising at least a Ge surface (). The method comprises, while heating the substrate () to a temperature between 550&#xb0; C. and 940&#xb0; C., exposing the substrate () to a nitrogen gas flow. The present invention furthermore provides a structure comprising a monocrystalline GeN layer () on a substrate (). The monocrystalline GeN formed by the method according to embodiments of the invention allows passivation of surface states present at the Ge surface ().

Growth of monocrystalline GeN on a substrate

Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 &#x3bc;mol/cmof one or more organometallic compounds containing Al, in a flow of less than 5 &#x3bc;mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Method for forming a group III nitride material on a silicon substrate

The present invention provides a method for depositing or growing a group III-nitride layer, e.g. GaN layer (), on a substrate (), the substrate () comprising at least a Ge surface (), preferably with hexagonal symmetry. The method comprises heating the substrate () to a nitridation temperature between 400&#xb0; C. and 940&#xb0; C. while exposing the substrate () to a nitrogen gas flow and subsequently depositing the group III-nitride layer, e.g. GaN layer (), onto the Ge surface () at a deposition temperature between 100&#xb0; C. and 940&#xb0; C. By a method according to embodiments of the invention, a group III-nitride layer, e.g. GaN layer (), with good crystal quality may be obtained. The present invention furthermore provides a group III-nitride/substrate structure formed by the method according to embodiments of the present invention and a semiconductor device comprising at least one such structure.

Deposition of group III-nitrides on Ge

The present invention is related to a device comprising a substrate comprising a silicon substrate having a porous top layer, a second layer on said top layer, said second layer made of a material comprising Ge, and a further layer of a Group III-nitride material on the second layer. The present invention further is related to methods of production and to intermediate or template devices highly suitable for the epitaxial growth of a high quality Group III-nitride layer.

Growing community of inventors

Scherpenheuvel-Zichem, Belgium

Stefan Degroote