Infineon Technologies Ag

Stefan Decker

Thorsten Meyer

Robert Illing

Christoph Kadow

Norbert Krischke

Michael Nelhiebel

Sven Lanzerstorfer

Robert Zink

Stefan Woehlert

Christian Djelassi

Thomas Detzel

Karl Hofmann

Kurt Matoy

Bernhard Auer

Arno Zechmann

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

Semiconductor device having a load current component and a sensor component

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

Semiconductor device including self-protecting current sensor

A semiconductor device comprises a semiconductor body. The semiconductor body comprises insulated gate field effect transistor cells. At least one of the insulated gate field effect transistor cells comprises a source zone of a first conductivity type, a body zone of a second, complementary conductivity type, a drift zone of the first conductivity type, and a trench gate structure extending into the semiconductor body through the body zone along a vertical direction. The trench gate structure comprises a gate electrode separated from the semiconductor body by a trench dielectric. The trench dielectric comprises a source dielectric part interposed between the gate electrode and the source zone and a gate dielectric part interposed between the gate electrode and the body zone. The ratio of a maximum thickness of the source dielectric part along a lateral direction and the minimum thickness of the gate dielectric part along the lateral direction is at least 1.5.

Semiconductor device and method of manufacturing the same

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration

By thermal oxidation a field oxide layer is formed that lines first and second trenches that extend from a main surface into a semiconductor layer. After the thermal oxidation, field electrodes and trench gate electrodes of power transistor cells are formed in the first and second trenches. A protection cover including a silicon nitride layer is formed that covers a cell area with the first and second trenches. With the protection cover covering the cell area, planar gate electrodes of lateral transistors are formed in a support area of the semiconductor layer.

Semiconductor device with power transistor cells and lateral transistors and method of manufacturing

Integrated circuit having field effect transistors and manufacturing method

Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.

Integrated circuit including power transistor cells and a connecting line

According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region.

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Munich, Germany

Stefan Decker