Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Imec Vzw

Katholieke Universiteit Leuven

Taiwan Semiconductor Manufacturing Comp. Ltd.

Katholieke Universitiet

Katholieke Universiteit Leuven, K.u. Leuven Research & Development

Stefan De Gendt

Tom Schram

Paul A Zimmerman

Cedric Huyghebaert

Bogdan Govoreanu

Lars-Ake Ragnarsson

Sven Van Elshocht

Steven Brems

Wim Deweerd

David Paul Brunco

Wilfried B Vandervorst

Matty Caymax

Marc Marcel Heyns

Anne S Verhulst

Roger Loo

Rita Rooyackers

Annelies Delabie

Joshua Tseng

Denis Shamiryan

Anne Vandooren

Mikhaïl Baklanov

Amirhasan Nourbakhsh

Daniele Leonelli

Adam Michal Urbanowicz

Thomas Nuytten

Ken Verguts

Zilan Li

Thomas Witters

Kazuhiko Yamamoto

Alessandra Leonhardt

Cesar Javier Lockhart De La Rosa

Peter Snee

Paul Zimmerman

A spot on a layer of a 2D semiconductor material deposited on a substrate is irradiated so as to generate excitons, so that photons are emitted from the layer. The photoluminescence spectrum is recorded for different values of the charge carrier concentration in the layer. The modulation of the charge carrier concentration may be realized by modulating the output power of the light source used to irradiate the sample. The relation is recorded between the ratio of the photoluminescence intensity of a first peak in the spectrum related to radiative recombination from indirect bandgaps to the intensity of a second peak in the spectrum related to radiative recombination from direct bandgaps, and the carrier concentration. This relation is fitted to a model of the ratio that takes into account multiple recombination mechanisms, radiative and non-radiative. From this process, the trap density within the bandgap is derived.

Method for measuring the trap density in a 2-dimensional semiconductor material

The disclosed technology generally relates to preparing two-dimensional material layers, and more particularly to releasing a graphene layer from a template substrate. According to an aspect, a method of releasing a graphene layer includes providing a template substrate on which the graphene layer is provided, the method comprising: subjecting the graphene layer and the template substrate to a water treatment by soaking the graphene layer and the template substrate in water such that water is intercalated between the template substrate and the graphene layer; and subjecting the graphene layer and the template substrate to a delamination process, thereby releasing the graphene layer from the template substrate.

Method of releasing graphene from substrate

A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.

Graphene based field effect transistor

A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material.

Method for fabricating a dual work function semiconductor device and the device made thereof

A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Scalable interpoly dielectric stacks with improved immunity to program saturation

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

One inventive aspect relates to a method for fabricating a high-k dielectric layer. The method comprises depositing onto a substrate a layer of a high-k dielectric material having a first thickness. The high-k dielectric material has a bulk density value and the first thickness is so that the high-k dielectric layer has a density of at least the bulk density value of the high-k dielectric material minus about 10%. The method further comprises thinning the high-k dielectric layer to a second thickness. Another inventive aspect relates to a semiconductor device comprising a high-k dielectric layer as fabricated by the method.

Method for fabricating a high-K dielectric layer

An improved reaction chamber cleaning process is provided for removing water residues that makes use of noble-gas plasma reactions. The method is easy applicable and may be combined with standard cleaning procedure. A noble-gas plasma (e.g. He) that emits high energy EUV photons (E&#x3e;20 eV) which is able to destruct water molecules to form electronically excited oxygen atoms is used to remove the adsorbed water.

Cleaning of plasma chamber walls using noble gas cleaning step

The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.

Atomic layer deposition method for depositing a layer

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Wijnegem, Belgium

Stefan De Gendt