Infineon Technologies Ag

Stefan Dankowski

Alexander Benedix

Wolfgang Ruf

Reinhard Dueregger

Reinhard Düregger

Matthias Lehr

Dominique Savignac

Axel Brintzinger

J&uuml;rgen Lindolf

Jochen M&uuml;ller

Ulrich Frey

Bernhard Lippmann

Tim Gutheit

Kamel Ayadi

A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Semiconductor package authentication feature

A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.

Memory system for network broadcasting applications and method for operating the same

To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines&#x2014;used in the process&#x2014;of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.

Method for testing semiconductor circuit devices

A method is provided for storing data in a memory device having memory cells arranged in memory cell rows and memory cell columns. The method can include a step for providing redundant memory cells in the memory device. The method can also include a step for localizing defective cells. Further, the method can include a step of accessing the redundant memory cells by means of a predeterminable access mode. The method can also include a step of bypassing defective memory cells of the memory device in a manner dependent on the predeterminable access mode during operation of the memory device for accessing redundant memory cells and for replacement by redundant memory cells. Further, the method can include a step for providing redundant memory cells for storing additional information describing a defect correction.

Method for storing data in a memory device with the possibility of access to redundant memory cells

The present invention relates to an interconnect structure for an integrated circuit ( ) having a first interconnect (B ; B &prime;; B &Prime;), which is composed of a plurality of interconnect sections (A -A ; A &prime;-A &prime;; A &Prime;-A &Prime;) lying in a first and a second interconnect plane (M , M ); and a second interconnect (B ; B &prime;; B &Prime;), which runs adjacent to the first interconnect (B ; B &prime;; B &Prime;) and which is composed of a plurality of interconnect sections (A -A ; A &prime;-A &prime;; A &Prime;-A &Prime;) lying in the first and second interconnect planes (M , M ); the first and second interconnects (B ; B &prime;; B &Prime;; B ; B &prime;; B &Prime;) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;, A &Prime;) of the first interconnect (B ; B &prime;; B &Prime;) which lie in the first interconnect plane (M ) run at least in sections beside the interconnect sections (A , A ; A &prime;; A &prime;; A &Prime;, A &Prime;) of the second interconnect (B ; B &prime;; B &Prime;) which lie in the second interconnection plane (M ), and that the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;, A &Prime;) of the first interconnect (B ; B &prime;; B &Prime;) which lie in the second interconnect plane (M ) run at least in sections beside the interconnect sections (A , A , A ; A &prime;, A &prime;, A &prime;; A &Prime;) of the second interconnect (B ; B &prime;; B &Prime;) which lie in the first interconnect plane (M ). The invention also provides a corresponding fabrication method.

Interconnect structure for an integrated circuit and corresponding fabrication method

According to one embodiment, a dynamic memory is provided. The dynamic memory can include a memory matrix having a plurality of memory cells arranged in rows and columns. The memory cells in a row can be connected by in each case one of a plurality of word lines. The memory cells in a column can be connected by in each case one of a plurality of bit lines. The dynamic memory can also include a sense amplifier for reading data from the memory cells via the plurality of bit lines. Further, the dynamic memory can include a row address decoder and a column address decoder for generating memory-internal address in a manner dependent on a memory-external address signal. The dynamic memory can also include a sequence control device for cyclically generating refresh addresses for carrying for carrying out a refresh operation of the memory cells.

Dynamic memory device and method for controlling such a device

The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate ( ); providing a metallization region ( ) comprising a first metal in the circuit substrate ( ); providing a first insulation layer ( ) above the metallization region ( ); forming an opening ( ) in the insulating layer ( ) in order to uncover at least part of the surface of the metallization region ( ); depositing a functional layer ( &prime;) above the resulting structure; depositing a second insulating layer ( ) above the resulting structure, in such a manner that the opening ( ) is filled; polishing-back of the second insulating layer ( ) and of the functional layer ( &prime;) in order to uncover the surface of the first insulating layer ( ); forming a contact ( &prime;) in the second insulating layer ( ) inside the opening ( ) in order to make contact with the functional layer ( &prime;); and providing an interconnect ( ) for electrical connection of the contact ( &prime;).

Growing community of inventors

Haar-Ottendichl, Germany

Stefan Dankowski