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Stefan Cserveny

Christian Piguet

Evert Dijkstra

Jean-Marc Masgonty

Fr&eacute;d&eacute;ric Robin

Vincent Von Kaenel

A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where &ldquo;Sel&rdquo; is a cell selection signal representative of the address, &ldquo;W&rdquo; is a write command, {overscore (W)} is a read command, &ldquo;D&rdquo; is the data to be written into the addressed cell and &ldquo;.&rdquo; indicates the AND function.

Random access memory

The invention concerns a power diverting circuit for creating a supply voltage for a signal processing circuit from a source of data signals each having a high or a low potential respectively corresponding to a first or a second logic state. The circuit comprises a first terminal for receiving the data signals, a second terminal for providing the supply voltage, a switch coupled between the first terminal and the second terminal for selectively connecting and disconnecting the first terminal and the second terminal, and an inverter for inverting the state of the data signals. The inverter, which has an input terminal connected to the first terminal and an output terminal for providing the inverted data signals to the signal processing circuit, is responsive to the state of the data signals received at the first terminal to control the operation of said switch means.

Power diverting circuit

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Epalinges, Switzerland

Stefan Cserveny