Imec Vzw

Imec

Katholieke Universiteit Leuven

Stichting Imec Nederland

Katholieke Universiteit Leuven, Ku Leuven R&d

Stefan Cosemans

Francky Catthoor

Julien Ryckaert

Gouri Sankar Kar

Wim Dehaene

Ann Witvrouw

Vibhu Sharma

Maliheh Ramezani

Komalan Manu Perumkunnil

Jos Huisken

Maryam Ashouei

Geert Van Der Plas

Maarten Rosmeulen

Praveen Raghavan

Zsolt Tokei

Steven Demuynck

Arnaud Furnemont

Peter Debacker

Jonas Doevenspeck

Ioannis Papistas

Woojin Kim

Yueh Chang Wu

Olivier Henry

Example embodiments relate to matrix-vector multiplications based on charge-summing memory cell strings. An example in-memory compute device for performing analog multiply-and-accumulate operations on a set of data inputs and a set of weight inputs includes a string of serially connected memory cells formed over a semiconductor channel structure, a source junction controllably connectible to one end of the string of memory cells via a string select switch, a readout circuit including a sense node controllably connectible to one end of the string of memory cells via a charge transfer switch, and control circuitry. The control circuitry is configured to apply pass mode signals, data input signals, and stop signals sequentially according to each memory cell's position along a string. The control circuitry is also configured to enable the string select switch and the charge transfer switch.

Matrix-vector multiplications based on charge-summing memory cell strings

A method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device is disclosed. The MTJ device is switchable between a first resistance state and a second resistance state. A first threshold voltage for switching the MTJ device from the second resistance state to the first resistance state is lower than a second threshold voltage for switching the MTJ device from the first resistance state to the second resistance state. The method includes applying a first voltage pulse across the MTJ device with an amplitude having an absolute value equal to or greater than the first threshold voltage and lower than the second threshold voltage, thereby setting the MTJ device to the first resistance state regardless of whether the MTJ device initially is in the first or second resistance state.

Memory device and method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, and an in-memory computing device including an array of the compute cells, are provided. In one aspect, the compute cell includes a set of input connectors for receiving modulated input signals representative of a sign and a magnitude of the data input, and a memory unit configured to store the ternary weight. A logic unit connected to the set of input connectors and the memory unit receives the data input and the ternary weight. The logic unit selectively enables one of a plurality of conductive paths for supplying a partial charge to a read bit line during a compound duty cycle of the set of input signals as a function of the respective signs of data input and ternary weight, and disables each of the plurality of conductive paths if at least one of the ternary weight and data input have zero magnitude.

Analog in-memory computing based inference accelerator

Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.

Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same

A storage device including a tape configured to store data is disclosed. The tape includes a plurality of first regions with a first dielectric constant and a plurality of second regions with a second dielectric constant that is higher than the first dielectric constant. The first regions and the second regions are arranged in an alternating manner along the length of the tape. Further, the storage device includes one or more actuators configured to apply an electrical field across the width of the tape, in order to move the tape in length direction. Further, the storage device includes one or more data heads configured to read and/or write data from and/or to the tape.

Storage device using a tape for storing data

A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

Method for manufacturing a magnetic tunnel junction device and device manufactured using such method

A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Method and device to reduce leakage and dynamic energy consumption in high-speed memories

A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

Buried interconnect for semiconductor circuits

A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node. A memory arrangement of such data storage cells is also disclosed, as well as methods for writing data to the data storage cells and for reading data from the data storage cells.

Non-volatile memory array using electromechanical switches for cell storage

The disclosed technology relates generally to electromechanical devices, and relates more specifically to a nanoelectromechanical switch device and a method for manufacturing the same. In one aspect, an electromechanical device includes a first electrode stack and a second electrode stack, both electrode stacks extending in a vertical direction relative to a substrate surface and being spaced apart by a gap. The electromechanical device additionally includes a third electrode stack comprising a beam extending in a vertical direction in the electrode gap and being spaced apart from the first electrode stack by a first gap, from the second electrode stack by a second gap, and from the substrate by a third gap; and a connector portion overlapping the first and second electrode stacks, wherein, in operation, the beam is movable in a first direction so as to electrically connect with the first electrode stack or in a second direction so as to electrically connect with the second electrode stack, and, in a rest position, the beam is isolated from the first and the second electrode stacks. Additionally, at least one of the first or second electrode stacks comprises two electrodes including a top electrode stacked over a bottom electrode, wherein the top and bottom electrodes are separated by an electrical insulator.

Vertical electromechanical switch device

A non-volatile memory arrangement comprising a plurality of cells is disclosed. In one aspect, each cell comprises a memory element and a read selector in series. Further, the memory element is a nano-electro-mechanical switch comprising an anchor, a beam fixed to the anchor, a first and second control gate, for controlling the position of the beam, a first output node against which the beam can be positioned. The cell also comprises a read selector comprising a first selector terminal, a second selector terminal, the first selector terminal connected to the first output node. The first respectively second control gates of switches of a same word are connected together by a first respectively second write word line serving as control gate.

Nano-electro-mechanical based memory

The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof

A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Local write and read assist circuitry for memory device

A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided.

Growing community of inventors

Mol, Belgium

Stefan Cosemans