International Business Machines Corporation

Stefan Buettner

Juergen Pille

Dieter F Wendel

Jens Leenstra

Wolfgang Penth

Werner Juchmes

Christian Schweizer

David Allen Hrusecky

Rolf Sautter

Uwe Brandt

Otto M Wagner

Friedrich C Wernicke

Guenter Mayer

Jurgen Pille

Torsten Mahnke

In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.

Reduced power consumption memory circuitry

A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.

Test interface for memory elements

An asymmetrical random access memory cell () including cross coupled inverters () which are driven at their nodes () by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (), wherein said cross coupled inverters () have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor () is provided in series to one of the pass-transistors () between one of the nodes () and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.

Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory

A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.

Device and method for decoding an address word into word-line signals

The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK , CLK ), which consist of at least first and second data input ports ( ) with together at least three data inputs (DATA , . . . , DATA DATA , . . . , DATA ) and at least one data output (OUT). The first clock (CLK ) controls whether data (DATA , . . . , DATA ) applied to the first data input ports ( ) is stored in or clocked through the latch ( ), the second clock (CLK ) controls whether data (DATA , . . . , DATA ) applied to the second data input ports ( ) is stored in or clocked through the latch, and either the first clock (CLK ) or the second clock (CLK ) clocks data into the latch at the same time.

Static logic compatible multiport latch

Static wordline redundancy memory device

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Sindelfingen, Germany

Stefan Buettner