International Business Machines Corporation

Stefan Bonsels

Thomas Pflueger

Friedrich Schroeder

Martin Padeffke

Cedric Lichtenau

Dieter F Wendel

Tobias Werner

Tobias Gemmeke

Thuyen Le

Alexander Albert Woerner

Antje Mueller

The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module () via the voltage supply line. The supply voltage is composed of a reference voltage and a number of additional voltage levels. The reference voltage is defined by a voltage source and controlled by the integrated circuit via the bus, and the number of additional voltage levels is determined by the integrated circuit and send to the voltage regulation module via the sense line. Further the present invention relates to a corresponding apparatus with a voltage regulation module and an integrated circuit.

Method for controlling the supply voltage for an integrated circuit and an apparatus with a voltage regulation module and an integrated circuit

A method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is partially built up by storage elements and/or logic circuits. At least one scan chain is formed as a series of selected storage elements and the other storage elements are used for the LBIST engine or a part of said LBIST engine in a testing mode. The scan chain is driven by a test pattern and the LBIST test case is testing those parts of the logic circuits corresponding to the storage elements of said scan chain.

Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit

A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage. The three stage circuit is switched to a low leakage state by a control signal feed via the control input and setting the two transistors in their off state resulting in a second stage with a floating common output filtered by the third stage via the control signal actively driven the data output to a specific logic value.

Circuit design methodology to reduce leakage power

A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.

Topology for a n-way XOR/XNOR circuit

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Stuttgart, Germany

Stefan Bonsels