Infineon Technologies Ag

Stefan Bergler

Alfred Lang

Thomas Baumann

Michael Mirbeth

Sascha Siegler

Jens Bargfrede

Gerhard Weber

A method and a device for checking a circuit path of a circuit for adherence to set-up and hold times are provided. A timing behavior of the circuit path is designated as being correct if at least one pair of set-up and hold times from predefined set-up and hold times that are for the circuit path does not produce any timing infringement in the circuit path. Otherwise, the timing behavior of the circuit path is classified as being defective. This decreases the number of circuit paths wrongly designated as being defective by the use of pairs of predefined set-up and hold times and decreases the chip area for buffers.

Method and device for checking a circuit for adherence to set-up and hold times

Methods and apparatuses for performing timing analyses of an electronic circuit are provided. Waveforms of signals in the circuit are determined, and timing checks are performed based on these waveforms.

Methods and apparatuses for timing analysis of electronics circuits

A method for estimating a terminal capacitance associated with a terminal of a cell of a digital circuit includes providing first and second capacitance values associated with an upper and lower bound, respectively, on the terminal capacitance, providing results of a timing analysis of the digital circuit, and determining an estimation value for the terminal capacitance based on the results of the timing analysis and at least one of the first and second capacitance values. A system for estimating a terminal capacitance includes a storage unit which stores the first and second capacitance values and a processor which performs a timing analysis of the digital circuit and determines an estimation value for the terminal capacitance based on the timing analysis and at least one of the first and second capacitance values.

System for estimating a terminal capacitance and for characterizing a circuit

According to the invention a characteristic property of an electronic circuit component depending on at least one variable (X, X) is approximated by an approximating function. This is accomplished by dividing a total range of said least one variable into a number of sub-ranges by inserting dividing nodes (), and approximating characterization data points () in each of the sub-ranges by an elementary function, wherein the elementary functions defined in the sub-ranges join together to form said approximating function defined in said total range. The approximation is accomplished such that the approximating function is continuously partial differentiable with respect to said at least one variable (X, X) in the dividing nodes ().

Method and system for characterizing electronic circuitry

A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Growing community of inventors

Munich, Germany

Stefan Bergler