Texas Instruments Corporation

Stefan Beierke

Dirk Preikszat

Norbert Asche

Issa Mahboobi Panahi

A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is formed as a loop antenna array configured to transmit and receive RFID signals. Further, the RFID tag includes a first test pad and second test pad formed on the integrated circuit die with the first test pad coupled to a first end of the antenna by a first interconnect and a second test pad coupled to the second end of the antenna by a second interconnect.

RFID tag having an integrated antenna coupled to test pads

A radio frequency identification (RFID) tag. In one embodiment, an RFID tag includes an integrated circuit die. The integrated circuit die includes circuitry configured to store information and transmit the stored information responsive to reception of a radio frequency (RF) signal. The integrated circuit die also includes an antenna coupled to the circuitry. The antenna is configured to transmit and receive RFID signals. Further, the antenna and the interconnects of the circuitry are formed of a same metal, and fabricated using a same semiconductor process.

RFID tag with integrated antenna

A control apparatus for controlling a three phase load apparatus. The control apparatus includes a voltage source inverter having a first pair of transistors, a second pair of transistors, and a third pair of transistors. Each such pair of transistors is connected serially between the terminals of a voltage source. The activation of a first transistor in each such pair of such transistors is effected by the application thereto of a first activation voltage, a second activation voltage and a third activation voltage, respectively, causing a first phase voltage, a second phase voltage and a third phase voltage, to be applied to a respective one of the three parts of the three-phase load apparatus. The selection and duration of activation of such first transistors during each of a continuing series of equal time periods T.sub.p is symmetrical about the mid-point of each of the time periods, and is represented by six non-zero vectors and two zero vectors. The control apparatus also includes a processor, and a bus coupled to the processor for communicating data between the processor and other control apparatus elements. The control apparatus also includes a counter coupled to the bus for providing a counter value counting from zero up to a value of one half of T.sub.p and then counting down to zero, for each of the equal time periods T.sub.p. A compare unit is also included, coupled to the bus, having a plurality of registers for the storage of transition count values corresponding to the transition times between the activations of the first transistors in accordance with predetermined space vectors, for comparing the counter value against the transition count values and providing respective transition timing signals when the counter value is the same as the transition count values. Finally, a state machine is included, coupled to the bus and to the compare unit for generating the first activation voltage, the second activation voltage and the third activation voltage and providing them to the voltage source inverter in response to the respective transition timing signals.

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Furth, Germany

Stefan Beierke