Agere Systems Inc.

General Electric Company

Lucent Technologies Inc.

At&t Bell Laboratories

Agere Syatems Inc.

Stefan Allen Siegel

John Christopher Kriz

Dipankar Bhattacharya

Bernard Lee Morris

Makeshwar Kothandaraman

Thaddeus John Gabara

Yehuda Smooha

Tony S El-Kik

Joseph E Simko

Jeffrey Jay Nagy

Anthony W Seaman

Michael L Snodgrass

Lisa Ann Peterson

A compensation circuit comprises a reference circuit including a reference NMOS device and a reference PMOS device. The reference circuit is operative to generate a first reference signal and a second reference signal, the first reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference NMOS device, and the second reference signal being a function of at least one of a process characteristic, a voltage characteristic and a temperature characteristic of the reference PMOS device. The compensation circuit further comprises a control circuit connected to the reference circuit. The control circuit is operative to receive the first and second reference signals and to generate one or more output signals for compensating for a variation in at least one of a process characteristic, a voltage characteristic and a temperature characteristic of at least one NMOS device and at least one PMOS device in a circuit to be compensated, which is connectable to the control circuit, in response to the first and second reference signals, respectively.

Reference compensation circuit

A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations

A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.

Semiconductor resistor

An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.

Voltage translator circuit for a mixed voltage circuit

A passive resistive element is provided in series with a digital variable impedance to produce a highly linear output impedance for a transmission path over a wide range of operating conditions.

Method and apparatus for controlling impedance

An apparatus and method is provided that improves the dynamic range of an optical transimpedance receiver. The receiver includes a photodetector, a transimpedance front end amplifier and a non-liner feedback. The non-linear feedback means consists of a Schottky diode and shunting the transimpedance resistor with a parasitic capacitor. A lead compensation network is further included in the feedback circuitry to provide stability to the non-linear circuit by advancing the phase shifting of the transimpedance front end by 45 degrees. By stabilizing the frequency off the circuit, the dynamic range is increased from 26.6 dB to 40 dB.

Optical transimpedance receiver with compensation network

A high-speed driver for LED data communications systems. A differentiator provides a turn-on and a turn-off pulse of current to the LED. The amount of charge delivered during turn-off is adjusted to sweep substantially all of the carriers from the LED without reverse-biasing the LED.

High-speed driver for an LED communication system or the like

An LED pulse shaping circuit is disclosed which is capable of providing improved rise time (using current peaking) and fall time (using charge extraction). The pulse shaping circuit consists of a conventional differential current switch coupled to a pair of switching elements and resistance elements. A first switching element is activated at the beginning of a pulse to provide for an initially increased drive current to the LED, the value of a first resistance element used to determined the level of the increased drive current. The current peaking thus results in decreasing the rise time of the LED. The remaining switching element and resistance are utilized, in conjunction with the differential current switch, to provide a reverse current flow through the LED at the end of the pulse. The charge extraction thus results in decreasing the fall time of the LED.

LED pulse shaping circuit

A receiver for a burst Manchester encoded composite optical digital signal has an interferometer comprising two fiber optic transmission lines. The lines differ in length so that they have time delays that differ by the period of the sync signal. Thus, the interferometer extracts the sync signal from the composite signal. The sync signal and a data signal are detected by photodiodes.

Receiver having an interferometer

A binary data receiver data modulated light signals and applies them to a photodetector for producing electrical data signals which are amplified and applied to a data decision circuit. The data decision circuit compares the instantaneous value of the amplified data signals with a fixed threshold to determine if a logic high or low level is received. A portion of the signal path between the photodetector and the data decision circuit is ac coupled, whereby the moment-to-moment variations of duty cycle of the signal due to the information content of the data causes variations in the peak excursions of the signal which may adversely affect the data decisions or processing of the data. Open-circuit correction of the average value is accomplished by a correction signal generator which receives an ac coupled data sample, and rectifies both positive-going and negative-going excursions relative to ground to produce positive and negative average value signals. The positive and negative average value signals are summed to produce a correction signal. The correction signal is either added to the ac coupled signal or controls the output offset voltage of a signal amplifier to correct the information-depending average-value variations at the data decision circuit.

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Fogelsville, PA, United States of America

Stefan Allen Siegel