Thomson Licensing

Dolby International Ab

Dolby Laboratories Licensing Corporation

Stefan Abeling

Holger Kropp

Thomas Brune

Axel Kochale

Wolfgang Klausberger

Johann Maas

Sven Kordon

Alexander Krueger

Johannes Boehm

Florian Keiler

Xiaoming Chen

Michael Drexler

Oliver Kamphenkel

Herbert Schuetze

The encoding and decoding of HOA signals using Singular Value Decomposition includes forming based on sound source direction values and an Ambisonics order corresponding ket vectors (|Y(&#x3a9;)) of spherical harmonics and an encoder mode matrix (&#x39e;). From the audio input signal (|x(&#x3a9;)) a singular threshold value (&#x3c3;) determined. On the encoder mode matrix a Singular Value Decomposition is carried out in order to get related singular values which are compared with the threshold value, leading to a final encoder mode matrix rank (r). Based on direction values (&#x3a9;) of loudspeakers and a decoder Ambisonics order (N), corresponding ket vectors (|Y(&#x3a9;)) and a decoder mode matrix (&#x3a8;) are formed. On the decoder mode matrix a Singular Value Decomposition is carried out, providing a final decoder mode matrix rank (r). From the final encoder and decoder mode matrix ranks a final mode matrix rank is determined, and from this final mode matrix rank and the encoder side Singular Value Decomposition an adjoint pseudo inverse (&#x39e;)of the encoder mode matrix (&#x39e;) and an Ambisonics ket vector (|a') are calculated. The number of components of the Ambisonics ket vector is reduced according to the final mode matrix rank so as to provide an adapted Ambisonics ket vector (|a&#x2032;). From the adapted Ambisonics ket vector, the output values of the decoder side Singular Value Decomposition and the final mode matrix rank an adjoint decoder mode matrix (&#x3a8;)is calculated, resulting in a ket vector (|y(&#x3a9;)) of output signals for all loudspeakers.

Methods and apparatus for higher order ambisonics decoding based on vectors describing spherical harmonics

Currently there is no simple and satisfying way to create 3D audio from existing 2D content. The conversion from 2D to 3D sound should spatially redistribute the sound from existing channels. From a multi-channel 2D audio input signal (x(t)) a 3D sound representation is generated which includes an HOA representation Formula (I) and channel object signals Formula (II) scaled from channels of the 2D audio input signal. Additional signals Formula (III) placed in the 3D space are generated by scaling (; Formula (IV)) channels from the 2D audio input signal and by decorrelating (; Formula (V)) a scaled version of a mix of channels from the 2D audio input signal, whereby spatial positions for the additional signals are predetermined. The additional signals Formula (III) are converted () to a HOA representation Formula (I).

Method and apparatus for generating from a multi-channel 2D audio input signal a 3D sound representation signal

Method and apparatus for higher order ambisonics encoding and decoding using singular value decomposition

The encoding and decoding of HOA signals using Singular Value Decomposition includes forming () based on sound source direction values and an Ambisonics order corresponding ket vectors (|Y(&#x3a9;5))) of spherical harmonics and an encoder mode matrix (&#x39e;). From the audio input signal (|&#x3c7;(&#x3a9;))) a singular threshold value (&#x3c3;) determined. On the encoder mode matrix a Singular Value Decomposition () is carried out in order to get related singular values which are compared with the threshold value, leading to a final encoder mode matrix rank (fin). Based on direction values (&#x3a9;) of loudspeakers and a decoder Ambisonics order (N), corresponding ket vectors (IY(&#x3a9;)) and a decoder mode matrix (&#x3a8;) are formed (). On the decoder mode matrix a Singular Value Decomposition () is carried out, providing a final decoder mode matrix rank (fin). From the final encoder and decoder mode matrix ranks a final mode matrix rank is determined, and from this final mode matrix rank and the encoder side Singular Value Decomposition an adjoint pseudo inverse (&#x39e;)of the encoder mode matrix (&#x39e;) and an Ambisonics ket vector (Ia') are calculated. The number of components of the Ambisonics ket vector is reduced () according to the final mode matrix rank so as to provide an adapted Ambisonics ket vector (|a&#x2032;). From the adapted Ambisonics ket vector, the output values of the decoder side Singular Value Decomposition and the final mode matrix rank an adjoint decoder mode matrix (&#x3a8;)is calculated (), resulting in a ket vector (|y(&#x3a9;)) of output signals for all loudspeakers.

High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO, . . . , FIFO Z) until the amount of collected data in a current buffer corresponds to a current one of the data blocks. Then, the data of the current data block from the current buffer are stored into memories connected to a current one of the memory buses, wherein the following buffered data block of the related data stream is later on stored into memories connected to a following one of the memory buses, the number of the following memory bus being increased with respect to the number of the current memory bus. These steps are repeated, also for the other ones of the data streams using other available ones of the buffers and other ones of the memory buses. In combination with a corresponding buffer control it is possible to allocate and use a minimum number of buffers in a flexible way.

Storing/reading several data streams into/from an array of memories

A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signal as synchronized clock signal, and wherein the control circuit is adapted to toggle between the n delay locked loop circuits, in a way that the phase of the internal clock signal is successively shifted according to the current phase shift between the internal clock signal and the reference clock signal.

Clock generation circuit

The present invention relates to a mass storage system with improved usage of buffer capacity, and more specifically to a mass storage system for real-time data storage with an embedded controller. According to the invention, the mass storage system has a first data path between a real-time data interface and a mass storage array, the first data path including a data buffer without access latency, and a second data path between an embedded processor and the mass storage array, wherein the data buffer without access latency is also used as a data buffer for non real-time data transfers between the embedded processor and the mass storage array.

Mass storage system with improved usage of buffer capacity

The present invention relates to a redundancy protected mass storage system with increased performance, and more specifically to a mass storage system with multiple storage units. According to the invention, the resources that are essentially provided for compensating the damage of one or more storage units are also used to enhance the system performance. For this purpose during reading or writing the storage system just waits for the responses of a minimum number of required storage units to start reading or writing, respectively.

Redundancy protected mass storage system with increased performance

In a storage medium, an address space is defined which is divided into a first area and a second area. According to the invention, at least one file is stored on the medium which is split into small data packets and large data packets. All small data packets are stored on said first area, and all large data packets are stored on said second area. A single file allocation table (FAT) is used and is small by having one entry per data packet.

Growing community of inventors

Schwarmstedt, Germany

Stefan Abeling