Alcatel

Alcatel N.v.

Stefaan Margriet Van Hoogenbemt

Peter P Reusens

Johan J Haspeslagh

Marc R De Langhe

An interfacing device (INT) which replaces M outgoing sets of bits out of N outgoing sets of bits (OS1, OS2, . . . , OSN) by M incoming sets of bits (IS1, IS2, . . . , ISM), M being smaller than N, includes:

Interfacing device to replace M sets of bits out of N sets of bits,

A digital phase locked loop arrangement is used in a desynchronizer demapping a plesiochronous stream from a synchronous bitstream is disclosed to remove jitter due to overhead gapping from the plesiochronous stream. To this end the part of the synchronous bitstream constituting the plesiochronous stream is written into a buffer memory (BUFF), the write address (WRADDR) of which is incremented at the rate of this plesiochronous part. The read address (RDADDR) for the buffer memory (BUFF) is derived from the write address (WRADDR) in the digital phase locked loop arrangement. Herein, a negative feedback for byte justifications in the synchronous bitstream and a positive feedback for bit justifications therein is provided so that byte justifications give rise to a lower change in the incrementing rate of the read address (RDADDR) but of longer duration, whereas bit justifications give rise to an increased change in this incrementing rate but of shorter duration.

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Mechelen, Belgium

Stefaan Margriet Van Hoogenbemt