Intel Corporation

Steen K Larsen

Francesc Guim Bernat

Kshitij Arun Doshi

Mark A Schmisseur

Daniel Rivas Barragan

Travis T Schluessler

Mazhar I Memon

Bryan E Veal

Daniel S Lake

Ramakrishna Huggahalli

Raj K Ramanujan

Eliezer Tamir

Ben-Zion Friedman

Vadim Makhervaks

Robert O Sharp

Kenneth G Keels

Brian S Hausauer

Rasika Subramanian

Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.

Techniques to control quality of service for end-to-end paths in a compute environment

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Reducing network latency during low power operation

Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.

Fabric encapsulated resilient storage

A technology is described for performing a multi-node storage operation. An example networked memory storage group coupled to a plurality of computing nodes through s network fabric can be configured to receive a transaction detail message from a master computing node that includes a transaction identifier and transaction details for a multi-node storage operation. Thereafter, storage operation requests that include the transaction identifier may be received from computing nodes assigned storage operation tasks associated with the multi-node storage operation. The networked memory storage group may be configured to determine that storage operations for the multi-node storage operation have been completed and send a message to the master computing node indicating a completion state of the multi-node storage operation.

Multi-node storage operation

A computing device, a method and a system to control power. The computing device is configured to be used as part of a network fabric including a plurality of nodes and a plurality of pooled accelerators coupled to the nodes. The computing device includes: a memory storing instructions; and processing circuitry configured to perform the instructions. The processing circuitry is to receive respective requests from respective ones of the plurality of nodes, the requests addressed to a plurality of corresponding accelerators, each of the respective requests including information on a kernel to be executed by a corresponding accelerator, on the corresponding accelerator, and on a performance target for execution of the kernel. The processing circuitry is further to, based on the information in said each of the respective requests, control a power supply to the corresponding accelerator.

Multi-criteria power management scheme for pooled accelerator architectures

Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.

Local and remote dual address decoding using caching agent and switch

Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.

Techniques for use of vendor defined messages to execute a command to access a storage device

An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A host operating system may reside, at least in part, in the system memory. The message may include both data and at least one descriptor associated with the data. The data may be included in the at least one descriptor. The circuitry also may signal the I/O controller that the writing has occurred.

Writing message to controller memory space

In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one request to access at least one portion of data. The at least one request may indicate, at least in part, at least one subset of the at least one portion of the data that is of relatively higher importance than one or more other subsets of the at least one portion of the data that are of relatively lower importance. The at least one request may be to request, at least in part, that the at least one subset be accessed prior to the one or more other subsets are accessed. The at least one request may be comprised, at least in part, in at least one packet in accordance with a protocol that permits variable packet size.

Generating and/or receiving, at least one data access request

A method includes, at a network interface controller receiving packets from a network connection for a set of multiple coupled processors, distributing received packets to each of a first set of the processors. In response to determining the change in network traffic, operation of the network interface controller is altered to distribute packets to a second set of the processors.

Altering operation of a network interface controller based on network traffic

Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be compressed before being transferred between various components of a computing system. For example, a packet payload may be compressed prior to transfer between network interface cards or controllers (NICs) and storage devices (e.g., including a main system memory and/or cache(s)), as well as between processors (or processor cores) and storage devices (e.g., including main system memory and/or caches). Other embodiments are also disclosed.

Growing community of inventors

Hillsboro, OR, United States of America

Steen K Larsen