Intel Corporation

Stavros Kalafatis

Alan Beecher Kyker

Robert D Fisch

Reynold V D'Sa

Rebecca E Hebda

Robert B Chaput

Gustavo P Espinosa

Micheal D Cranford

Brinkley Sprunt

Gad S Sheaffer

Scott D “Dion” Rodgers

A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded processor. Specialized event select control registers are programmed to control the selection, masking and qualifying of events to be monitored. Events are qualified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

Qualification of event detection by thread ID and thread privilege level

A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.

Method and apparatus for thread switching within a multithreaded processor

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The predetermined quantity of the instruction information may be equal to or greater than a minimum quantity of instruction information for a full instruction of a first instruction set.

Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction

A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A flow marker within instruction information for the first thread received at the instruction information source is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the detection of the flow marker, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A stall condition relating to the first thread within a processor pipeline of the multithreaded processor is detected. The elapsing of a predetermined time interval subsequent to the detection of the stall condition is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread and the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer.

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition

A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. A branch instruction within the instruction information of the first thread to be dispatched from the instruction information source is also detected. Responsive to the detection of the branch instruction and the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information of a second thread from the instruction streaming buffer is thus commenced.

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction

A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. An absence of a flow of instruction information of the first thread into the instruction information source from an upstream source in a processor pipeline is detected. The elapsing of a predetermined time interval subsequent to the detection of the absence of the flow of the instruction information is also detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, and responsive to the elapsing of the predetermined time interval, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.

Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

System and method of maintaining and utilizing multiple return stack buffers

System and method of maintaining and utilizing multiple return stack

An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

System and method for processing a plurality of branch instructions by a

A digital phase-locked loop having a jitter limited to one-half of a period of the reference clock comprises a generator circuit and a control circuit. The input clock is defined by a plurality of rising edges and falling edges. The generator circuit receives a reference clock and generates the output clock. The phase of the output clock is one of a plurality of selectable phases such that the difference in phases between the output clock and the input clock is limited to one-half of a period of the reference clock once the DPLL locks to the input clock. The control circuit receives the input clock, the reference clock, and the output clock and provides a selection input to the generator circuit to make the phase of the output clock selectable upon each rising edge and upon each falling edge of the input clock.

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Portland, OR, United States of America

Stavros Kalafatis