Xilinx, Inc.

Other

Stanley Yuanshih Chen

Parag Upadhyaya

Yohan Usthavia Frans

Hsung Jai Im

Mayank Raj

Jinyung Namkoong

Chuan Xie

Jun-Chau Chien

Kee Hian Tan

Lei Zhou

Winson Lin

Wenfeng Zhang

Yipeng Wang

Zhaowen Wang

Sandeep Kumar

Scott D McLeod

Ping Chuan Chiang

Sukruth Pattanagiri Giriyappa

Muqseed Mohammad

Sukruth Pattanagiri

Yi Zhuang

Scott D Mcleod

An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

Circuits and methods for wavelength locking of optical receiver WDM filters

A near-field sensor method and device for obtaining biomedical information is disclosed. A transmission-line aperture arrangement configured to guide electromagnetic waves and emit near-field fringing energy, is placed near the skin. The transmission line is excited at a narrow-band Gigahertz frequency. The near-field fringing energy emitted by the sensor device penetrates at least partially into the skin and underlying blood vessels, and this energy is partially absorbed and partially phase shifted in a time varying manner according to the changes in tissue physiology. The status of the sensor device is monitored over a plurality of time intervals, and changes in both the phase and the amplitude of the signals passing though the transmission line are used to determine biomedical information such as heart rates, PTT, blood pressure, and glucose levels. Various transmission-line configurations, and various reference transmission-line methods to reduce low-frequency noise, are also discussed.

Gigahertz frequency fringing near-field biomedical sensor

A near-field sensor method and device for obtaining cardiovascular information is disclosed. A transmission-line aperture arrangement configured to guide electromagnetic waves and emit near-field fringing energy, is placed near the skin. The transmission line is excited at a narrow-band Gigahertz frequency. The near-field fringing energy emitted by the sensor device penetrates at least partially into the skin and underlying blood vessels, and this energy is partially absorbed and partially phase shifted in a time varying manner according to the changes in physiology of the skin. The status of the sensor device is monitored over a plurality of time intervals, and changes in both the phase and the amplitude of the signals passing though the transmission line are used to determine the cardiovascular information such as heart rates. Various transmission-line configurations, and various reference transmission-line methods to reduce low-frequency noise, are also discussed.

Gigahertz frequency fringing near-field cardiovascular sensor

Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.

Temperature-locked loop for optical elements having a temperature-dependent response

A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

Circuit for and method of receiving signals in an integrated circuit device

An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

Ultra-low-power injection locked oscillator for IQ clock generation

A frequency divider circuit () includes a frequency sub-divider () to provide a frequency divided clock, a delay circuit () configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit () configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

High speed frequency divider

A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

Circuit for and method of receiving a signal in an integrated circuit device

In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

Growing community of inventors

Cupertino, CA, United States of America

Stanley Yuanshih Chen