Unisys Corporation

Stanley P Naddeo

Steven T Hurlock

John E Black

Daniel F Wright

In a data processing system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and second level cache can control the processor return path at a given time, an improvement comprises a queue disposed between an output of the first level cache and the processor return path to buffer data output from the first level cache so that the first level cache can continue to process memory requests even though the second level cache has control of the processor return path.

Method and apparatus for prevent stalling of cache reads during return of multiple data words

As copies of data from a main memory are stored in a cache memory of a processor of a computer system as original data, the addresses of those copies are stored successively in a queue. Once the depth of the queue is reached, the storage of each new address in the queue causes a previously stored address to be output from the queue. For each address output from the queue, the corresponding original data in the cache is returned to the main memory. The amount of original data stored in the cache is therefore limited. Preferably, the queue comprises a first-in, first-out queue, and the depth of the queue is programmable.

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Wayne, PA, United States of America

Stanley P Naddeo