Motorola Corporation

Freescale Semiconductor,inc.

Stanley Michael Filipiak

Terry Grant Sparks

Yeong-Jyh Tom Lii

T P Ong

Avgerinos V Gelatos

David L O'Meara

Robert W Fiordalice

Michael P Woo

Kevin D Lucas

Craig S Lage

Hisao Kawasaki

Ritwik Chatterjee

Andrew G Nagy

Mousumi Bhat

Johnson O Olowolafe

Larry E Frisa

Carol M Gelatos

Jian Feng Chen

Mehul D Shroff

Ted R White

Tab Allen Stephens

Michael D Turner

Varughese Mathew

Paul Grudowski

Rabiul Islam

Bernard J Roman

Sam S Garcia

Faivel S Pintchovski

Wayne M Paulson

Kathleen C Yu

Ramnath Venkatraman

Jung-Hui Lin

Jeffrey T Wetzel

John C Flake

Rajan Nagabushnam

John R Yeargain

Kirk J Strozewski

Yongjoo Jeon

John C Arnold

James Edward Vasek

Phillip E Crabtree

Yuri Solomentsev

Cesar M Garza

Chad Weintraub

Mark G Fernandes

Lynne M Michaelson

Gregor Braeckelmann

Bradley P Smith

Bruce Allen Boeck

William D Darlington

Edward Acosta

Cindy K Goldberg

Christopher D Pettinato

Wayne D Clark

Yeong Jyh Lii

Zhi-Xiong Jiang

Yongloo Jeon

A method is provided for creating a barrier layer () on a substrate comprising a dielectric layer () and a metal interconnect (). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to a second plasma selected from the group consisting of oxidizing plasmas and reducing plasmas. Next, a barrier layer is created on the treated substrate.

Dual plasma treatment barrier film to reduce low-k damage

A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region, wherein the layer includes hydrogen and (ii) using gases containing hydrogen in a plasma for the subsequent device processing, wherein the semiconductor device is subject to an undesirable device characteristic alteration by hydrogen incorporation into the region. The method further comprises forming a hydrogen barrier layer overlying the region, wherein the hydrogen barrier layer prevents substantial migration of hydrogen made available due to the subsequent device processing into the underlying region. The method further includes performing the subsequent device processing.

Semiconductor device with hydrogen barrier and method therefor

A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.

Method of forming an interlayer dielectric

A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.

Method of forming a semiconductor device having a diffusion barrier stack and structure thereof

A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Method of making a semiconductor device using treated photoresist

An etch stop layer located over a plasma enhanced nitride (PEN) layer. Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.

Plasma enhanced nitride layer

Dummy features () are formed within an interlevel dielectric layer (). Passivation layers (and) are formed by electroless deposition to protect the underlying conductive regions (and) from being penetrated from the air gaps (). In addition, the passivation layers (and) overhang the underlying conductive regions (and), thereby defining dummy features (and) adjacent the conductive regions (and). The passivation layers (and) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Method for forming a passivation layer for air gap formation

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects ( and ), wherein each local interconnect ( ) cross couples the inverters of the SRAM and is formed within a single opening ( ). Also, interconnect portions ( ) of word lines are laterally offset from silicon portions ( ) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Semiconductor device, memory cell, and processes for forming them

A method for forming a semiconductor device is disclosed in which a fluorinated silicon dioxide layer is formed over a semiconductor substrate. A first undoped silicon dioxide layer, with a thickness preferably less than approximately 50 nanometers, is then formed on the fluorinated silicon dioxide layer with a PECVD process wherein a power ratio of a high frequency power source of the PECVD reactor to a low frequency power source is preferably in a range of approximately 0.2:1 to 0.4:1. In one embodiment, a second undoped silicon dioxide layer may be formed prior to forming the fluorinated silicon layer. The second undoped silicon dioxide, the fluorinated silicon dioxide layer, and the first undoped silicon dioxide layer may be formed sequentially in the same plasma enhanced chemical vapor deposition process chamber during a single chamber evacuation cycle. The first undoped silicon dioxide layer is preferably characterized as having a refractive index greater than approximately 1.460. The first undoped silicon dioxide layer has a compressive stress that is approximately 1.5 times greater than the fluorinated silicon dioxide layer. In one embodiment, the first undoped silicon dioxide layer has a ratio of silicon atoms to oxygen atoms that is greater than 1:2. In one embodiment, the first undoped silicon dioxide layer and the fluorinated silicon dioxide layer are chemically vapor deposited using a TEOS precursor.

Reduced water adsorption for interlayer dielectric

A hardmask layer (,) is formed over insulating layers (,and,), and an antireflective layer (,) is formed overlying the hardmask layer (,). A resist layer (,) is formed overlying the antireflective layer (,), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (,). The exposed surface portion of the antireflective layer (,) and portions of the hardmask layer (,) are etched to expose a surface portion of the insulating layers (,and,), and a feature opening (,) is formed in the insulating layers (,and,). A conductive material (,) is deposited to fill the feature opening (,), and portions of the conductive material (,) lying outside the opening are removed.

Process for forming a combination hardmask and antireflective layer

A tPEN layer (,) having a tensile stress is formed over a conductive gate stack (,) provided on a semiconductor substrate. Following the formation of the conductive gate stack (,), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (,) is formed and patterned to form a gate (,).

Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode

The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.

Semiconductor device having a titanium-aluminum compound

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (,and,), wherein each local interconnect (,) cross couples the inverters of the SRAM and is formed within a single opening (,). Also, interconnect portions (,) of word lines are laterally offset from silicon portions (,) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region

In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (,) on a semiconductor substrate (,). The dielectric layer (,) is then patterned to form interconnect openings (,). A layer of copper (,) is then formed within the interconnect openings (,). A portion of the copper layer (,) is then removed to form copper interconnects (,) within the interconnect openings (,). A copper barrier layer (,) is then formed overlying the copper interconnects (,). Adhesion between the copper barrier layer (,) and the copper interconnects (,) is improved by exposing the exposed surface of the copper interconnects (,) to a plasma generated using only ammonia as a source gas.

Copper interconnect structure and method of formation

A inlaid interconnect is formed in a semiconductor device (30). A first interlayer dielectric (ILD) 40 is deposited and etched to form a via opening (44). An etchstop layer (42) is deposited on ILD (40). A second ILD (45) is deposited on etchstop layer (42) in a manner so that a pinch-off region (46) is formed to prevent substantial deposition of the ILD material into via opening (44). While a small deposit (47) of ILD material may form within the via opening, this can be easily removed in a subsequent etch of ILD (45) which forms a trench opening (48) in ILD (45). A metal layer (50) is then deposited and polished to form a metal interconnect having a trench portion (52) and a via portion (54) in device (30). The present invention avoids the need for a substantial over-etch to clear the via, and avoids the need to form a thick resist mask to form the via opening, while maintaining a controlled via diameter.

Method for forming an inlaid via in a semiconductor device

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Pflugerville, TX, United States of America

Stanley Michael Filipiak