Mosaid Technologies Corporation

Stanley Jeh-Chun Ma

Peter P Ma

Peter B Gillingham

Valerie L Lines

Abdullah Ahmed

Robert McKenzie

A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

Matchline sense circuit and method

A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Multiple match detection circuit and method

A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. the circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

A duty cycle regulator derives from an input clock of arbitrary duty cycle, an output clock having an adjustable duty cycle of similar frequency. The duty cycle regulator includes a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set, providing a high signal to the delay unit, after which the delay interval resets the bistable circuit to provide a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

Duty cycle regulator

A duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal having an arbitrary duty cycle. Once the input clock signal is received, an output clock storage element is switched to a first state upon detecting a transition in the input clock signal for driving the output clock signal to a first signal level. The output clock storage element is then switched to a second state after a delay interval equal to a fraction of the period for driving the output clock signal to a second signal level. The fraction of the period can be programmed to a pre-selected value.

Duty-cycle regulator

A duty cycle regulator derives from an input clock of arbitrary duty cycle an output clock having an adjustable duty cycle of similar frequency. The duty cycle regulator includes a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set giving high signal to the delay unit, which after the delay interval resets the bistable circuit to give a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

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Gloucester, Canada

Stanley Jeh-Chun Ma