Integrated Device Technology, Inc.

Stanley Hronik

Mark W Baumann

A method and apparatus for fast PLL initialization have been disclosed where control of a VCO is based on a selected control signal which is based upon either a comparison signal or a prespecified signal.

Method and apparatus for fast PLL initialization

A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output of the differential amplifier is coupled to a flip flop. The flip flop has an output indicating when a bounce threshold is exceeded.

Method and apparatus for ground bounce and power supply bounce detection

A method and apparatus for adjusting PLL and/or DLL timing offsets have been disclosed.

Method and apparatus for adjusting PLL and/or DLL timing offsets

A method and apparatus for cross-point detection in devices have been disclosed where each leg of a differential signal is compared to a reference voltage and time lags for each are noted in crossing the reference voltage and this information is used to identify characteristics of the differential signal.

Method and apparatus for cross-point detection

A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output of the differential amplifier is coupled through a diode to a sample and hold circuit which is coupled to an analog to digital converter.

A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

Random access memory architecture and serial interface with continuous packet handling capability

A synchronous memory circuit is capable of double data transfer rate per clock cycle, 100% bus utilization (i.e., no idle clock cycles in bus turn arounds), and has only one clock cycle of latency in each of read and write burst operations. The memory circuit has a data bus, at least two memory blocks (), a multiplexer () for receiving two read data items from respective two memory blocks in a read burst operation and allowing one of the two read data items to be provided on the data bus half a clock cycle after the read burst operation is initiated and allowing the other one of the two read data items to be provided on the data bus one clock cycle after the read burst operation is initiated, and two registers () for storing respective two write data items provided on the data bus in a first write burst operation wherein one of the two write data items is written to one of the two memory blocks at the initiation of a next write burst operation following the first write burst operation and the other one of the two write data items is written to the other one of the two memory blocks half a clock cycle after the initiation of the next write burst operation, wherein in two consecutive clock cycles the two write data items are capable of being transferred to the memory circuit via the data bus and the two read data items are capable of being transferred from the memory circuit via the data bus.

Double data rate synchronous SRAM with 100% bus utilization

A quad data rate RAM ( ) in accordance with the invention is a burst synchronous RAM with separate data buses (Data-In, Data-Out) for read and write data. Data can be transferred on both buses and on both the rising and the falling edge of the clock (CLK). Operating at the maximum throughput, four data items are transferred per clock cycle. In one embodiment, data is written to or read from the RAM in bursts of four data items. The RAM includes four independent internal RAM blocks ( ). in a write burst, (i) a write address, (ii) control signal(s), and (iii) four write data items are sequentially presented to the respective four internal RAM blocks at the respective four clock edges of two consecutive clock cycles. A read burst is carried out similar to a write burst except that there is a one clock cycle latency between the four read data items and the burst address.

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Sunnyvale, CA, United States of America

Stanley Hronik