U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

St-Ericsson Sa

Stanley D Brotherton

John M Shannon

Nigel David Young

John R A Ayres

David J McCulloch

Carl Glasse

Carole A Fisher

John R Ayres

Michael J King

Audrey Gill

Frnak W Rohlfing

A photo transistor has an active region spaced from a source by barrier. A drain is laterally spaced from the active region. Light incident on the active region creates electron-hole pairs. Holes accumulate at the barrier and modulate the effective barrier height to electrons. A gate reset voltage then is applied to gate which lower the barrier allowing the holes to escape.

Phototransistor with source layer between barrier layer and photosensitive semiconductor layer

Phototransistor with source layer between barrier layer and photosensitive semiconductor layer and a gate layer for controlling the barrier height of the barrier layer

A method of making a source-gated transistor is described, in which a gate () is provided on substrate () followed by gate insulator () and semiconductor layer (). The layer is patterned to align the source with the gate () using photoresist () and back illumination through the substrate () with the gate () acting as a mask. The distance between source and drain may also be self-aligned using a spacer technique.

Transistor manufacture

A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer ( ) is etched back underneath a mask layer ( ). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam ( ).

Electronic device manufacture

The invention provides a method of manufacturing a large-area electronic device, for example a flat panel display, comprising thin-film circuit elements, and also laser apparatus for crystallizing a portion of a semiconductor thin-film (1) with a beam (11) of set energy. The energy of the beam (11) is set in accordance with the output from a light detector (22) to regulate the crystallization of a device portion (3,4 and/or 5) of a semiconductor thin film (1) at which the beam (11) is subsequently directed with its set energy. The light detector (22) monitors the surface quality of a previously crystallized portion (2). In accordance with the present invention, the light detector (22) is located at a position outside the specular reflection path (25) of the light returned by the surface area of the crystallized portion (2) and detects a threshold increase (D) in intensity (I.sub.s) of the light (26) being scattered by the surface area of the crystallized portion. This threshold increase (D) occurs when the energy (E.sub.p) of the beam (11) is increased sufficiently to cause the onset of surface roughening.

A method of manufacturing a flat panel display or other electronic device comprising thin-film circuit elements includes the steps of depositing and patterning a less conductive film (2) and metal film (1) to provide a laminated conductor, depositing and patterning semiconductor material to provide a circuit element island (50), and then directing an energy beam (100) towards the island (50) to crystallise the semiconductor material for the island (50). In order to protect the metal film (1) from the energy beam (100) the less conductive film (2) is deposited on the metal film (1), is of a semiconductor material absorptive of the energy beam (100), and is deposited to a thickness which is larger than its melt depth (d) when heated by the energy beam (100) during the crystallisation of the semiconductor material of the island (50). When the metal film (1) is not protected in this way, then the stresses occurring can degrade the integrity of the metal film (1) and any overlying insulating films (3) and/or semiconductor islands (50).

Method of manufacturing a thin-film electronic device with a laminated

A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the density of charge carrier traps. Source and drain electrodes (6 and 7) contact opposite ends (5a,5b) of the channel region (5), and a gate electrode (8) is provided at one major surface (4a) of the semiconductor layer (4) for controlling a conduction channel of one conductivity type in the polycrystalline channel region (5) to provide a gateable connection between the source and drain electrodes (6 and 7). An area (50) of the polycrystalline channel region (5) spaced from the electrodes (6,7,8) of the transistor (1) and lying adjacent to the other major surface (4b) of the semiconductor layer (4) is doped with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent to the other major surface (4b).

Thin film field effect transistor having a doped sub-channel region

In the manufacture of a liquid-crystal display or other large area electronic device, thin-film transistors are formed on a substrate (10) from a thin film (1) of disordered semiconductor material which accommodates the transistor channel regions and has a high density of trapping states. A masking pattern (13) masks areas of the semiconductor film (1) where the thin-film transistors are to be formed. The unmasked areas of the film (1) are etched away to leave the semiconductor film bodies for the transistors. The resulting transistors are found to have an undesirable leakage current through the channel region, even after adopting several prior art measures to reduce the high leakage. By implanting a dopant stripe (5) along their edges, the present invention reduces leakage currents along the edges of the channel region in the etched disordered semiconductor material (1). The implantation of ions (15) is effected through bevelled edge portions (13) of the masking pattern (13) so as to form the dopant stripe (5) across the thickness of the semiconductor film material (10). The thickness of the masking pattern (13) is sufficient to mask against implantation of the ions (15) except below the bevelled edge portions (14). The technology is compatible with the use of a substrate (10) not able to withstand temperatures of more than about 700.degree. C.

Manufacture of electronic devices comprising thin-film transistors using

A thin-film transistor circuit (10) has a main thin-film transistor (Trl) and an input gate protection device (11) formed by first and second subsidiary thin-film transistors (Tr2) and (Tr3) connected in series and to the gate electrode (1) of the main thin-film transistor (Tr1). The gates (4 and 7) and one of the main electrodes (5 and 9) of each of the first and second subsidiary thin-film transistors (Tr2 and Tr3) are connected. The other main electrodes (6 and 8) of the first and second subsidiary thin-film transistors (Tr2 and Tr3) are connected together so that only one of the first and second subsidiary thin-film transistors (Tr3 and Tr3) conducts when a voltage above a threshold voltage is applied to the gate electrode (1) of the main thin-film transistor (Tr1). The first and second subsidiary thin-film transistors (Tr2 and Tr3) have channel regions (20) of a length (L) selected for causing breakdown of the other one of the first and second subsidiary thin-film transistors (Tr2 and Tr3) when a given voltage greater than the threshold voltage is applied to the gate electrode (1) of the main thin-film transistor (Tr1), thereby rendering both the first and second subsidiary thin-film transistors (Tr2 and Tr3) conducting.

Thin-film transistor circuit

A plasma and heating treatment is carried out to reduce the density of charge carrier traps adjacent the interface of an insulating layer of a thermally grown silicon dioxide and a semiconductor body. During this plasma and heating treatment, the device is covered with an additional layer of silicon containing hydrogen, such as silane, for example, and this additional layer protects the insulating layer from direct bombardment of the plasma. During and/or after the plasma treatment, heating of the structure is at about 400.degree. C. or less. After the plasma and heating treatment, the additional layer is removed from at least most parts of the semiconductor device structure.

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Forest Row, United Kingdom

Stanley D Brotherton