Intel Corporation

Stanley Chen

Ankush Varma

Vivek Garg

Krishnakanth Venkata Sistla

Andrew J Herdrich

Dean A Mulla

Eric J DeHaemer

Nikhil Gupta

Nazar Syed Haider

Ripan Das

Adwait Purandare

Yogesh Bansal

Suresh Chemudupati

Eric Dehaemer

Aman Sewani

Rupal Parikh

Nilanjan Palit

Pavithra Sampath

Ujjwal Gupta

Nikethan Shivanand Baligar

Johan Van De Groenendaal

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

Register interface for computer processor

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

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Portland, OR, United States of America

Stanley Chen