Ramtron International Corporation

Agilent Technologies, Inc.

Stanley C Perino

Sanjay Mitra

George Argos, Jr

Thomas E Davenport

Holli Harper

A multi-threshold optical binning method for classifying the image quality of an optical sensor is presented. In accordance with the invention, a sensor tester causes a sensor pixel image to be generated by a sensor under test. The sensor pixel image is comprised of a plurality of pixels, each represented by an associated quantized intensity level. The quantized intensity level of a pixel may fall into one of a first pixel class, a second pixel class, or a third pixel class, for example, a dark pixel class, a dim pixel class, and an acceptable pixel class. An image filter processes the sensor pixel image, filtering but all pixels that fall within the acceptable pixel class, to generate a defective pixel map. The defective pixel map includes those pixels which have a quantized intensity level that falls within the first and/or second pixel class but not the third pixel class.

Test efficient method of classifying image quality of an optical sensor using three categories of pixels

A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H,O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion

A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

Yield enhancement technique for integrated circuit processing to reduce

Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array. The electrical cycling operation restores the symmetry and location of the hysteresis loop. The ferroelectric capacitor is then returned to the virgin state by a depoling operation. The electrical depoling operation is achieved by writing each capacitor in the array to a logic one and a logic zero at the full five volt power supply level initially, and then repeating each write cycle at decreasing power supply levels. The writing cycles are continued until the power supply is reduced to a minimum functional level and the polarization on the capacitors has been substantially removed.

Ferroelectric capacitor renewal method

A semiconductor manufacturing method is directed to forming a ferroelectric film, and in particular a ferroelectric film of the bismuth layer structure type, that has a significant component of reversible polarization perpendicular to the plane of the electrodes. The manufacturing method is conducted at low temperatures on commercially suitable electrodes and is compatible with conventional CMOS fabrication techniques. A ferroelectric strontium-bismuth-tantalate ('SBT') film is formed using two sputtering targets. A first sputtering target is comprised primarily of bismuth oxide (Bi.sub.2 O.sub.3) and a second sputtering target is comprised primarily of SBT. An initial layer of bismuth oxide is formed on the bottom electrode of a ferroelectric capacitor stack. The initial layer of bismuth oxide is directly followed by a sputtered layer of SBT. A second layer of bismuth oxide is then applied and the layers are alternated in a 'layer cake' fashion containing a plurality of layers until a desired thickness of the film is attained. At the end of the deposition, a crystallization anneal is performed to make the film ferroelectric. Once the ferroelectric film is in place, the top electrode is formed and the remaining processing steps are completed.

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Ft. Collins, CO, United States of America

Stanley C Perino