Intel Corporation

Cisco Technology, Inc.

Cisco Systems Inc.

Bolt Beranek and Newman Inc.

Stanley A Lackey, Jr

Sanjeev Jain

Gary S Muntz

William R Crowther

C Philip Levin

Daniel C Tappan

A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Request queuing system for a PCI bridge

An improved SRTS clock recovery system of a network node that adjusts the range of a received source RTS sample and a locally generated destination RTS sample to compensate for inherent characteristics of a network system. In addition, the improved system extends the range of the RTS samples to properly interpret large phase differences between a source node clock and transmit clock generated by the network node. This novel technique for interpreting source and destination RTS samples enables the improved network node to accurately recover a source clock frequency from a network transmission in a highly stressed network system. Specifically, the SRTS clock recovery system includes an RTS sample interpreter having a slope determinator for determining the expected average change in source and destination RTS samples over time. A slope compensator of the interpreter scales the range of RTS sample slopes to compensate for this expected average change in samples, thereby increasing the range of usable RTS sample slope values, while a range extender increases the number of phase values that the RTS sample slopes represent to accommodate large phase differences between the source and destination clock frequencies.

SRTS clock recovery system for use in a highly stressed network

A destination station receives from a network a data packet that is transmitted as a plurality of cells and separately encodes each of the received cells, to produce associated, individual c-bit partial CRC remainders, where c is the number of bits in the CRC remainder associated with the packet. These partial CRC remainders correspond to the respective contributions that the cells make to the packet CRC pattern. The encoder appends the partial CRC remainders to the cells, and the station then stores them in an associated memory and links the individual cells to previously stored cells from the same packet with pointers. Once all the cells of a packet are encoded and stored, the destination station retrieves appended partial CRC remainders from the memory, and provides the remainders to a partial CRC encoder. The encoder manipulates the partial remainders and produces a packet CRC remainder. If the CRC packet is error-free, this packet CRC remainder matches the predetermined CRC pattern associated with the CRC code.

Encoder for use in asynchronous transfer mode systems

The classifier device disclosed herein analyzes message headers of the type which comprise a sequence of bit groups presented successively. The device employs a read/write memory for storing at a multiplicity of addresses, an alterable parse graph of instructions. The parse graph instructions include node instructions which comprise opcodes in association with respective next address characterizing data and terminator instructions which comprise identifying data for previously characterized header types. A logical processor responds to a node instruction read from memory either by initiating another memory read at a next address which, given the current state of the processor, is determinable from the current node instruction and the current header bit group or by outputting data indicating recognition failure if no next address is determinable. The logical processor responds to a terminator instruction by outputting respective header identifying data. Accordingly, for a previously characterized header type, a corresponding pattern of node instruction and a terminator instruction can be written into memory thereby enabling the device to identify the respective header type in a time which is essentially proportional to the length of the header and thus also to the time of presentation of the header. The parse graph can be updated dynamically during the operation of the classifier.

Growing community of inventors

Groton, MA, United States of America

Stanley A Lackey, Jr