Digital Equipment Corporation

Stanley A Lackey

Richard Lee Sites

Dileep P Bhandarkar

Reinhard C Schumann

Kim A Meinerth

Frank C Bomba

William N Johnson

Jeffrey W Mitchell

Le T Nguyen

J J Grady, Iii

David A Stoner

A memory subsystem including a read-only memory (ROM), a random access read/write memory (RAM) and a selection system for selecting the output of one of the memories for use by downstream circuitry. The selection of the output is based on input address signals so that the contents of the RAM can substitute for the contents of selected locations in the ROM. If a substitution is to be made, an entry is made in a content addressable memory, which stores addresses for which the RAM output is to be substituted for ROM output. A test system is provided to verify the contents of the content addressable memory.

Memory subsystem

A bus interface unit for connecting a processor to a memory to form a digital data processing system. The storage locations in the memory are grouped in pages each having a selected access rights mode which regulates access to the data stored therein by the programs, each of which has a selected access rights mode. The access rights are assigned on a page by page basis. If an access request from a program requires transfers to multiple locations, the processor will normally perform an access verification on the first location while it is in the first transfer operation, and then perform the transfer operation and successive transfer operations. If the transfer operations require accesses to separate pages in memory, a microtrap operation is performed and the processor performs access verifications on locations in both pages before performing any transfers.

Access verification arrangement for digital data processing system which

One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.

Cache invalidation mechanism for multiprocessor systems

A special instruction processor, such as a floating point accelerator processor, that processes a special class of instructions. Each instruction identifies the number of operands to be processed as well as the number of data words required to be transferred for each operand. The central processing unit retrieves and decodes each instruction, and transfers the special instructions to the special instruction processor. Both processors decode the special instructions to determine the numbers of operands and data words to be transferred. The central processing unit retrieves the data words from memory and transmits them to the special instruction processor. The special instruction processor processes the instruction and signals the central processor when finished. The central processor then causes the special instruction processor to transmit the processed data back to the central instruction processor.

Special instruction processing unit for data processing system

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Stanley A Lackey