Intel Corporation

Stanislav Shwartsman

Zeev Sperber

Igor Yanover

Robert Valentine

Raanan Sade

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Bret L Toll

Jesus Corbal

Menachem Adelman

Dan Baum

Shlomo Raikin

Lihu Rappoport

Rinat Rappoport

Yuri Gebil

Alexander F Heinecke

Barukh Ziv

Gal Ofir

Pavel I Kryukov

Milind Baburao Girkar

Sreenivas Subramoney

Guy Patkin

Adi Yoaz

David M Durham

Simon Rubanovich

Michael Lemay

Jayesh Gaur

Anant V Nori

Jared Warner Stark, Iv

George Leifman

Liron Zur

Manjunath Shevgoor

Yiftach Gilad

Kamil Garifullin

Gilbert A Neiger

Ravi L Sahita

Vedvyas Shanbhogue

Hong Wang

Barry E Huntley

Andrew V Anderson

Ron Gabor

Joseph Nuzman

Michael Mishaeli

Niranjan L Cooray

Robert S Chappell

Ronak Singhal

Ehud Cohen

Ofer Levy

Ido Ouziel

Oleg Margulis

Vineeth Mekkat

Lev Makovsky

Shankar Balachandran

Sourabh Alurkar

Ron Shalev

Ron Rais

Elad Shtiegmann

Alexandr Titov

Efraim Rotem

Michael E Kounavis

Santosh Ghosh

David J Sager

Ilan Pardo

Nir Rosenzweig

Sergej Deutsch

Theodros Yigzaw

Fernando Latorre

Larisa Novakovsky

Pedro Lopez

Deep K Buch

Arijit Biswas

Sebastien Hily

Franck Sala

Ryan Carlson

Gavri Berger

Steffen Kosinski

Mark Dechene

Omar M Shaikh

Adarsh Chauhan

Alex Gerber

Andrey Kluchnikov

Varun Mohandru

Jared W Stark

Assaf Zaltsman

Evgeni Krimer

Muhammad Taher

Li-Gao Zei

Yulia Kurolap

Swaraj Sha

Tomer Weiner

Sumeet Bandishte

Pooja Roy

Melih Ozgul

Ori Lempel

Sudhanshu Shukla

Levy Ofer

Ethan Kalifon

Tom Aviram-Rosenfeld

Jaroslav Topp

Jonathan Edwards

An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

Region aware delta prefetcher

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

Systems, methods, and apparatuses for matrix operations

Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.

Device, method and system to predict an address collision by a load and a store

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

Systems, methods, and apparatuses for tile store

System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

System, method, and apparatus for enhanced pointer identification and prefetching

Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.

Hardware for split data translation lookaside buffers

Systems, methods, and apparatuses for tile load

An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.

Apparatus and method for store pairing with reduced hardware requirements

Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

Systems, methods, and apparatuses for zeroing a matrix

In one embodiment, a processor of a cryptographic computing system includes data cache units storing encrypted data and circuitry coupled to the data cache units. The circuitry accesses a sequence of cryptographic-based instructions to execute based on the encrypted data, decrypts the encrypted data based on a first pointer value, executes the cryptographic-based instruction using the decrypted data, encrypts a result of the execution of the cryptographic-based instruction based on a second pointer value, and stores the encrypted result in the data cache units. In some embodiments, the circuitry generates, for each cryptographic-based instruction, at least one encryption-based microoperation and at least one non-encryption-based microoperation. The circuitry also schedules the at least one encryption-based microoperation and the at least one non-encryption-based microoperation for execution based on timings of the encryption-based microoperation.

Microprocessor pipeline circuitry to support cryptographic computing

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

Embodiments detailed herein relate to matrix operations. In particular, embodiment of broadcasting elements are described. For example, some embodiments describe broadcasting a scalar to all configured data element positons of a destination matrix (tile). For example, some embodiments describe broadcasting a row to all configured data element positons of a destination matrix (tile). For example, some embodiments describe broadcasting a column to all configured data element positons of a destination matrix (tile).

Systems, methods, and apparatuses for tile broadcast

Growing community of inventors

Haifa, Israel

Stanislav Shwartsman