Synopsys, Inc.

Stanislav Margolin

Gagan Vishal Jain

Johnson Adaikalasamy

Vivek Gaur

Chengdong Jiang

The independent claims of this patent signify a concise description of embodiments. A method is provided for parallel simulation using synchronization during simulation. The method comprises executing a plurality of threads in parallel, identifying a first event block and a second event block of a circuit design, calculating a minimum delay (minDelay) based on a current simulation time, scheduled times for execution of the first event block and the second event block, and causal delays (CausalDelay) of the first event block and the second event block, and scheduling a next synchronization point based on the minimum delay, the next synchronization point being a next simulation time at which the plurality of threads synchronize to a common clock. This Abstract is not intended to limit the scope of the claims.

Event-level parallel simulation using dynamic synchronization

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

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Andover, MA, United States of America

Stanislav Margolin