Silicon Bandwidth, Inc.

The Panda Project

Other

Quantum Leap Packaging, Inc.

Silicon Bandwith Inc.

Stanford W Crane, Jr

Maria M Portuondo

Lakshminarasimha Krishnapura

Myoung-soo Jeon

Kevin J Link

Moises Behar

Arindum Dutta

Yun Li

Edward V Cruz

Charley T Ogata

Shaun Fynn

Maurice Bizzarri

Bill Ahearn

Willard Erickson

Zsolt Horvath

Daniel J Michalski

Vicente D Alcaria

Dan Fuoco

Joshua G Nickel

Josh Nickel

Vincent R Razo

Daniel Larcomb

Barry P Sween

Bruce Alan Smith

Hunter T Foy

Jose Emmanuel Schutt-Aine

Ton-Yong Wang

Richard J Schneebeli, Jr

Patrick Codd

Roy K Lee

Daniel Fuoco

William Cross

James Allan

Bruce Smith

Stephen G Burks

Aaron Lown

Andreas C Cangellaris

Jon P Otis

Lei-Ming Yang

Jennifer Colegrove

Matthew E Doty

Edward R Vanderslice

Vincent Alcaria

A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

Backplane system having high-density electrical connectors

A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.

Die package for connection to a substrate

A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts. A semiconductor die carrier may also include an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die carrier from a lower surface of the insulative substrate and an internal portion located within the semiconductor die carrier at an upper surface of the insulative substrate; a semiconductor die; and a layer of conductive material in contact with conductive portions of the semiconductor die and also in contact with the internal portions of the leads.

Semiconductor chip carrier affording a high-density external interface

Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.

Hermetic seal

A capacitor structure may be incorporated into an interposer or substrate associated with an IC chip to stabilize the input/output signals, such as power and ground, between the IC chip and a printed circuit board. In accordance with one embodiment, the capacitor structure may include a plurality of individual capacitors connected together to form a monolithic capacitor blade having a length, width, and height, wherein each of the length and height of the blade spans multiple of the individual capacitors. The blade includes multiple electrical conductive paths extending the height of the capacitor blade. According to another embodiment, the capacitor structure includes multiple interleaved power and ground layers separated by insulating layers. The power layers connect to power leads and the ground layers connect to ground leads.

Decoupling capacitor for an integrated circuit and method of manufacturing thereof

Optoelectronic packaging assemblies for optically and electrically interfacing a protected electro-optical device or system to both an optical fiber and to external circuitry. Such assemblies are comprised of body components that are comprised of plastic that coated or plated with a conductive material. Electrical contact pins in the form of transmission lines are used to couple external electrical signals with the package. The optoelectronic packaging assemblies are dimensioned with small cavities and with steps, breaks, walls, and/or fins molded into the body components. The optoelectronic packaging assemblies further include an optical input receptacle for receiving an optical ferrule and an optical fiber. The optoelectronic packaging assembly provides for cooling, such as by heat sink fins and/or a thermal-electric-cooler. The transmission line pins and body components are dimensioned to mate with a standardized circuit board having transmission line traces.

High performance optoelectronic packaging assembly

A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads. A method of manufacturing a semiconductor die carrier includes the steps of individually manufacturing a plurality of electrically conductive leads without use of a lead frame; extending a plurality of the electrically conductive leads from at least one of a plurality of electrically insulative side walls; positioning a semiconductor die such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and electrically connecting the semiconductor die to corresponding ones of the electrically conductive leads.

Prefabricated semiconductor chip carrier

A modular connector assembly includes a modular frame having a first holes, second holes, and third holes formed at evenly spaced intervals. A plurality of modular interconnect components, fixable within the modular frame, have a back surface projection formed thereon. Each modular interconnect includes a contact housing made of electrically insulating material, an exterior of the contact housing comprising first and second side surfaces, a back surface, and a top surface. Contact signal pins are fixed within and electrically insulated from the contact housing.

Modular coaxial electrical interconnect system having a modular frame and electrically shielded signal paths and a method of making the same

A lead insertion machine includes a substrate supply, a conductive lead supply, and an lead insertion mechanism. The conductive leads are inserted into lead passages formed in side walls of the substrate. Also disclosed is a method of manufacturing a semiconductor die carrier including the steps of forming a plurality of conductive leads, forming a substrate for holding a semiconductor die, the substrate having a plurality of insulative side walls defining an exterior surface of the substrate, each of the side walls having a plurality of lead passages formed therethrough, and simultaneously inserting at least one of the conductive leads into the lead passage of one of the side walls for retention therein and at least one other of the conductive leads into the lead passage of another of the side walls for retention therein.

Apparatus for and method of manufacturing a semiconductor die carrier

A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.

Packaged semiconductor device for radio frequency shielding

A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.

Semiconductor die package having mesh power and ground planes

A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.

Micro grid array semiconductor die package

Growing community of inventors

Boca Raton, FL, United States of America

Stanford W Crane, Jr