Koninklijke Philips Corporation N.V.

St&eacute;phane Mutz

Hugues De Perthuis

Thierry Nouvet

A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Arrangement with a plurality of processors having an interface for a collective memory

A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.

Growing community of inventors

Caen, France

Stéphane Mutz

Growing community of inventors

Caen, France

St&eacute;phane Mutz

Stéphane Mutz