STMicroelectronics

St&eacute;phane Monfray

Thomas Skotnicki

Alexandre Villaret

Catherine Mallardeau

The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor

A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N&plus; doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

Growing community of inventors

Grenoble, France

Stéphane Monfray

Growing community of inventors

Grenoble, France

St&eacute;phane Monfray

Stéphane Monfray