Stmicroelectronics S.a.

St&eacute;phane Bouvier

Andrew Cofler

Laurent Wojcieszak

Bruno Fel

Laurent Ducousso

A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Execution of a computer program

A computer system for executing instructions predicated on guard indicators included in the instructions. The instructions include normal instructions, which are executed if the guard indicator is true and branch instructions, which are executed if the guard indicator is false. The computer system is operable in a branch shadow mode for comparing the guard indicator of the branch instruction with the guard indicator included in subsequent instructions and for continuing to supply instructions if the guard indicators match and for preventing supply of instructions if the guard indicators do not match. The computer system is also operable to disable the branch shadow mode when the branch instruction has been determined such that the branch is taken or not by resolving the status of the guard indicator.

Branching in a computer system

A decode unit ( ) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry ( ) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX ,MUX ) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector ( ) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

Growing community of inventors

Sassena{overscore (g)}e, France

Stéphane Bouvier

Growing community of inventors

Sassena{overscore (g)}e, France

St&eacute;phane Bouvier

Stéphane Bouvier