Other

Realnetworks Gmbh

Vivo Software, Inc.

Mips Technologies, Inc.

Staffan Ericsson

Bernd Girod

William James Dally

Robert Gelinas

W Patrick Hays

Sol Katzman

Nikolaus Farber

Mary Deshon

Nikolaus F&auml;rber

Yuriy A Resnik

Sam Rosen

James Flach

Oliver Jones

Yuriy A Resznik

John Bruder

A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.

High performance RISC instruction set digital signal processor having circular buffer and looping controls

A method for generating a digital motion video sequence at a plurality of bit rates uses a transitional coding source when switching between bitstreams having different bit rates during transmission of a video sequence. The transitional data may be frames coded using reconstructed frames reconstructed for a first bitstream using the characteristics of the second bitstream. These 'low bit rate insert frames,' or LBIFs, contain the image characteristics of a signal coded at the lower bit rate. With a bitstream having a higher bit rate being periodically coded using an LBIF, a point of image continuity between the two bitstreams is provided. Thus, switching from one bitstream to the other at this point in the video sequence minimizes the production of artifacts caused by differences in bit rate. In another embodiment of the invention, a separate set of transitional data is created, taking the form of 'switch' frames, or S-frames. The S-frames are typically the difference between a frame of a first bitstream and a frame of a second bitstream. These frames are inserted into the decoded bitstream during the transition from one bitstream to the other, and compensate for any visual artifacts that might otherwise occur due to the difference in bit rate of the two bitstreams.

Method and apparatus for providing scalable pre-compressed digital video with reduced quantization based artifacts

A method for generating a digital motion video sequence at a plurality of bit rates uses a transitional coding source when switching between bitstreams having different bit rates during transmission of a video sequence. The transitional data may be frames coded using reconstructed frames reconstructed for a first bitstream using the characteristics of the second bitstream. These &ldquo;low bit rate insert frames,&rdquo; or LBIFs, contain the image characteristics of a signal coded at the lower bit rate. With a bitstream having a higher bit rate being periodically coded using an LBIF, a point of image continuity between the two bitstreams is provided. Thus, switching from one bitstream to the other at this point in the video sequence minimizes the production of artifacts caused by differences in bit rate. In another embodiment of the invention, a separate set of transitional data is created, taking the form of &ldquo;switch&rdquo; frames, or S-frames. The S-frames are typically the difference between a frame of a first bitstream and a frame of a second bitstream. These frames are inserted into the decoded bitstream during the transition from one bitstream to the other, and compensate for any visual artifacts that might otherwise occur due to the difference in bit rate of the two bitstreams.

A method is provided for performing a fast Discrete Cosine Transform (DCT) and a fast Inverse Discrete Cosine Transform (IDCT) in a software implementation. The method provided exploits symmetries found in both the DCT and IDCT. As a result of the symmetries found in the DCT and IDCT, both transforms may be performed using a combination of look-up tables and butterfly operations, thus employing only a small number of additions and subtractions and no multiplications. Furthermore, there is provided an aspect of the present invention which exploits the excess precision available in current central processing units (CPUs) relative to the precision required by the DCT and IDCT calculations.

Method and apparatus for performing fast discrete cosine transforms and

An image processing system operates at reduced resolution to reduce computational complexity while remaining fully compatible with full resolution decoders. A video input signal is subsampled and encoded at the resulting lower resolution. The encoded signal is filled with zero terms to produce an encoded signal having the same number of terms as a full resolution encoded signal. In a motion-compensated hybrid coder, the decoder section also includes a subsampling system, so that the reconstructed video signal is produced at the same resulting lower resolution. The encoder section and the decoder section are each inverse functions of the other, eliminating a drift problem associated with prior systems.

Image signal coder operating at reduced spatial resolution

A method is provided for performing a fast 3-coefficient Discrete Cosine Transform (DCT) in a software implementation. The method provided exploits symmetries and statistical properties of the coefficients found in the DCT. As a result of the symmetries and statistical distribution of coefficients typically found in the DCT of typical images in image processing applications, the 3-coefficient DCT may be readily performed using as few as three input sample values from an input image block. The method selects the samples from locations in the image block where they are at peaks of the basis functions for the coefficients included, thus maximizing noise immunity. The method also provides for switching between performing the 3-coefficient DCT and a full (or other) DCT as required by image quality. Finally, the method may be generalized to perform a reduced coefficient DCT of any number of coefficients less than all coefficients in a complete output block.

Method and apparatus for performing fast reduced coefficient discrete

A method of processing a digital signal wherein multiple signal values are simultaneously operated upon in a single register. The register is not segmented in hardware, but is segmented by operation of a controlling computer software program. The controlling computer software arranges the digital signal in a computer memory in such a manner as to permit the register to be loaded with a plurality of digital samples, each having a precision less than the total precision available in the register. The method may include steps to partially compensate for errors introduced by carries from one segment of the register to another segment of the register, when necessary.

Parallel processing of digital signals in a single arithmetic/logic unit

A computer teleconferencing method and apparatus are provided which permits transmission of video image sources including both computer display images and other video images. The apparatus may include at a local teleconferencing site a personal computer having a video graphics adapter, a monitor and a digital telephone interface. The digital telephone interface is used to establish communications with a remote teleconferencing site. The apparatus may further include a video camera and a video capture system connected into the personal computer. The method may include steps of capturing snapshots of a computer display image, converting those snapshots to a digital television form, and compressing and transmitting the digital television signal to the remote teleconferencing site.

Growing community of inventors

Brookline, MA, United States of America

Staffan Ericsson