Telefonaktiebolaget Lm Ericsson (publ)

Staffan Ek

Henrik Sjöland

Tony Påhlsson

Lars Sundström

Sven Erik Mattisson

Stefan Mikael Andersson

Fenghao Mu

Christian Elgaard

Anders Carlsson

Jim Svensson

Roland Strandberg

Martin Anderson

Aravind Tharayil Narayanan

Stefan Andersson

An integrated, distributed, multiple Phase Locked Loop (multi-PLL) system locks the frequency and phase of multiple secondary PLLs to that of a primary PLL. The VCOs in all PLLs receive both first and second control signals. The primary PLL's primary VCO control signal is generated conventionally. using a reference periodic signal input, and is output to all secondary PLLs: hence the secondary PLLs operate at the primary PLL frequency. The primary PLL also outputs its divided periodic signal. Each secondary PLL compares its local divided periodic signal to the one received from the primary PLL (rather than to a reference signal input) in its phase locking loop. generating a secondary VCO input that locks the secondary PLL circuit phase to that of the primary PLL circuit. Selected secondary PLLs can be set to a phase offset from the primary PLL, such as by controlled DC current injected into the charge pump output. Phase noise generated by the primary PLL VCO is detected and corrected by one or more secondary PLLs in a second charge pump circuit that outputs a correction current having an inverse polarity. The correction currents are summed, and a correction loop filter generates a third VCO control signal which is provided to the second primary VCO input to correct the phase noise. Either the charge pumps scale output current (1/N) or the correction loop filter scales impedance (1/N) to account for the number (N) of secondary PLLs generating correction currents. A common mode voltage circuit may monitor selected VCO control signals of all PLLs. and maintains the common mode input level within a predetermined voltage range.

Multiple PLL system with phase locking and phase noise cancellation

A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

Phase-locked loop

A plurality of Phase Locked Loops, PLL (), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL () is connected to a phase error averaging circuit (), which calculates an average phase error (C), and distributes it back to each PLL (). In each PLL (), two loop filters () with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.

Multiple PLL system with common and difference mode loop filters

A phase locked loop arrangement () beamforming comprises two or more phase locked loops. The loops include a phase comparator () and an adjustable charge pump arrangement () having a loop filter () and charge pump current source () with an adjustment input (&#x3d5;) connected to the loop filter () to inject an adjustable charge pump current into the loop filter. A constant current source () is configured to inject a first predetermined charge current into the loop filter (). The adjustable charge pump arrangements () are connected to the respective phase comparators () to provide a voltage control signal (vctrl) to an oscillator () of the respective phase adjustable phase locked loop () in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (f, f) based on an adjustment signal applied to the adjustment input (&#x3d5;).

Phase locked loop arrangement, transmitter and receiver and method for adjusting the phase between oscillator signals

An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f, f, f, f).

Transciever circuit

A fractional-N frequency synthesizer circuit is disclosed. It comprises a frequency divider circuit configured to receive a first oscillation signal having a first frequency, to receive a control word indicating a divisor, and to frequency divide the first oscillation signal with the divisor to generate a second oscillation signal having a second frequency, lower than the first frequency. It also comprises a modulator circuit configured to generate a sequence of control words to the frequency divider circuit. The modulator circuit comprises a set of memory elements configured to store an internal state of the modulator circuit in response to a first control signal and to restore the internal state of the modulator circuit in response to a second control signal, thereby enabling a time shift of the sequence of control words. A communication circuit, a communication apparatus, and a method are also disclosed.

Frequency synthesizer

A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

System for phase calibration of phase locked loop

A circuit for calibration measurements comprises a first and a second current source arranged to provide current outputs; a resistor connected between the first current source and a reference voltage; a capacitor connected between the second current source and the reference voltage; a discharge switch connected in parallel with the capacitor and arranged to selectively discharge the capacitor; a comparator circuit arranged to compare voltages across the resistor and the capacitor and output a signal when voltage across the capacitor reaches the voltage across the resistor; and a controller having a clock signal input and connected to the output of the comparator circuit. The controller is arranged to control the discharge switch to discharge the capacitor, change state of the switch to enable charging of the capacitor and count clock signal pulses until the comparator provides the signal when voltage across the capacitor reaches the voltage across the resistor, wherein the controller is arranged to determine a calibration measurement from counted number of clock signal pulses. A method, computer program and electronic device are also disclosed.

Circuit for calibration measurements, method, computer program, and electronic device

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Electronic circuit, phase-locked loop, transceiver circuit, radio station and method of frequency dividing

A digital solution for phase control of an output of a phase-locked loop (PLL) () is provided to achieve a desired phase shift at the output of the PLL (). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Digital phase controlled PLLs

An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.

Frequency divider, phase-locked loop, transceiver, radio station and method of frequency dividing

A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed. The quadrature phase detector comprises a first circuit arranged to collect a first state value indicating an inner state of a first quadrature signals generating frequency divider circuit of a first frequency synthesizer of the plurality of frequency synthesizers and a second state value indicating an inner state of a second quadrature signals generating frequency divider circuit of a second frequency synthesizer of the plurality of frequency synthesizers, a second circuit arranged to determine from the first state value and the second state value whether quadrature signals of the first frequency synthesizer and quadrature signals of the second frequency synthesizer are in-phase or out-of-phase, and a third circuit arranged to provide an output signal indicating whether the quadrature signals of the first frequency synthesizer and the quadrature signals of the second frequency synthesizer are in-phase or out-of-phase.

Quadrature phase detector circuit, quadrature phase corrector, multi-antenna radio circuit, radio station and method

The programmable frequency control system presented herein provides frequency programmability and phase noise reduction for signals generated by a plurality of frequency programmable phase-locked loops (PLLs). In general, a modulated data stream input to each of the plurality of PLLs controls the frequency of the signal output by the PLLs. The solution presented herein reduces the phase noise by introducing a time shift to the modulated data stream applied to at least some of the PLLs so that at least some of the PLLs receive time-shifted versions of the modulated data stream relative to other PLLs. In so doing, the solution presented herein decorrelates the quantization noise generated by the plurality of frequency programmable PLLs.

Fractional PLLs with low correlation

A voltage modulator () comprises a multi-level switched capacitor modulator () connected in parallel with a switched voltage regulator (). An output of the multi-level switched capacitor modulator and an output of the switched voltage regulator are combined, or both connected to an output node, to generate an output voltage. The voltage modulator has an input node to receive at least one input signal and further comprises a control unit () arranged to control the switched voltage regulator and the multi-level switched capacitor modulator such that the output voltage follows the input signal.

Voltage modulator

An analog phase-locked loop (PLL) is disclosed, comprising a voltage controlled oscillator (VCO); a frequency divider having its input connected to an output of the VCO; a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO. The PLL further comprises a second phase detector arranged to detect a number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and provide an output signal based on the number of cycles in phase difference; and a second charge pump connected to an output of the second phase detector and arranged to provide a charge per detected phase error, based on the output of the second phase detector, to the loop filter. A radio circuit, a communication device and a communication node are also disclosed.

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Lund, Sweden

Staffan Ek