Nortel Networks Corporation

Pmc-sierra, Inc.

Northern Telecom Limited

Applied Micro Circuits Corporation

Pmc-sierra Us, Inc.

Stacy W Nichols

David Alan Brown

Maged E Beshai

Heng Liao

Todd D Morris

David G Stuart

Norman Allan Lyon

Shahram Davari

Vernon Robert Little

Alan Charles Coady

Blake Toplis

Deborah Ann Frischknecht

Kevin Huscroft

Sameer Gandhi

Biniam Mesfin

Julian J Cheesman

Burt Christian

Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.

Discrete time compensation mechanisms

Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.

Feedback priority modulation rate controller

A method and apparatus for building a packet grooming and aggregation engine is disclosed. The grooming and aggregation engine can be applied to the network for providing flexible aggregation and service multiplexing functions. A method and apparatus achieves the intended function that is easy to implement and easy for the network operator to manage, yet provides enough flexibility to mix and match various services at the edge node of the network. One specific embodiment of the patent is an Ethernet over SONET mapping system where user traffic is aggregated and groomed into SONET transport virtual concatenation channels.

Method and apparatus for packet grooming and aggregation

Methods, systems, and apparatus for processing packet fragments for reassembly into packets. Datastreams containing packet fragments are received and data corresponding to different channels are segregated. For each channel, data is then aggregated to recreate packet fragments. Once the fragments are recreated, they are, if required, resequenced using a two-tier memory mapping structure where only pointers, and not the fragments, are manipulated. After resequencing fragments to reassemble the packet, the reassembled packet is dispatched to its ultimate destination. The present invention also provides a method of load balancing between multiple links when packet fragments are transmitted from a fragmenting node through a multiple link bundle.

Reassembly engines for multilink applications

A telecommunications switch for switching protocol data units across communications links connecting the switch into a communications network and supporting multiple service types concurrently is disclosed. The switch includes an ingress processor for receiving protocol data units from a communications link, an egress processor for transmitting protocol data units onto another communications link, and a switching fabric for routing protocol data units from the ingress processor to the egress processor. The switch includes a structure of queues and schedulers that is arranged to provide concurrent class-based and flow-based queuing and scheduling of the protocol data units. This arrangement allows an amount of switching bandwidth to be guaranteed to protocol data units belonging to a given flow and allows classes of service within the flow to be allocated a relative proportion of that bandwidth. The structure is re-configurable in its interconnection of queues and schedulers via a link list in which pointers to the queues and schedulers are stored and updated as required.

Telecommunications switches and methods for their operation

A node in a packet network such as an ATM network receives a plurality of traffic classes and outputs them to an output link. The invention relates to a technique of scheduling the traffic classes in a time linked fashion at the node based on the bandwidth allocated to each traffic class. Traffic scheduling based strictly on priority may not satisfy delay and loss guarantees of traffic classes when there are many classes with many different priority levels. The rate based scheduling in a time-linked fashion solves these problems by limiting the bandwidth to which each class is accessible. According to one embodiment, the invention uses timeslot values and a linked list of the traffic classes.

Time linked scheduling of cell-based traffic

A multi-stage switch includes a plurality of switching elements for routing cells from input components to output components. Internal switch logic routes incoming cells to the output components in the same temporal order as they are received from the input components, and sequentially activates the switching elements to distribute the cells evenly within the switch.

Multi-threaded, multi-cast switch

Systems and methods consistent with the invention write and read data cells to and from a bank of cell buffer memories. The system includes a plurality of memory units for storing data cells. An address memory outputs a memory address and a memory selecting unit selects one of the plurality of memory units based on the outputted memory address. The system then performs a read or write operation at the outputted memory address of the selected memory unit. The system may write data cells to one memory unit while at the same time reading data cells from one of the other memory units.

Methods and systems for storing cell data using a bank of cell buffers

Methods, systems, and networks for tracking multicast cell copies in a switch. The switch includes a plurality of output ports each having an associated output port register, and a port memory controller for receiving a bit map on the enqueue of a cell into the switch. The bit map includes a bit for each output port register. The port memory controller writes to each output port register the bit from the bit map for that port register. The value of a bit in an output port register indicates whether a copy of the enqueued cell is to be transmitted from the output port associated with that output port register.

Method and apparatus for port memory multicast common memory switches

In a multicast cell counting methodology, the use of banked memories for enqueuing and dequeuing a multicast cell count value spreads the memory accesses over multiple memories, yielding a reduction in the number of per memory accesses per cell cycle. A cell count value, representing the number of cell copies to be multicast, is written to a first memory on a cell enqueue, and retrieved from the first memory after a first cell dequeue. The cell count value is decremented to reflect the first cell dequeue, and transferred to a second memory.

ATM switch which counts multicast cell copies and uses a second memory for a decremented cell count value

Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Parallel service-rate controllers in ATM switches

Large-scale service-rate regulators for ATM switching

A method for scheduling low delay-jitter cell transmissions for multiple streams of Asynchronous Transfer Mode (ATM) traffic from a node is disclosed. Cells belonging to multiple streams of virtual circuits (VCs) and virtual paths (VPs) are stored in the node's memory. A link controller scans a time-space map to determine when a given stream will be sampled and its cells transmitted from the memory out over a link. The time-space map is comprised of time-slots whose spatial positions within the map correspond to times at which cells can be transmitted. A scattering technique, based on reverse-binary or other mapping schemes, ensures that each given stream occupies time-slots that are well-spaced within the time-space map. This ensures that cells belonging to a given stream are transmitted at well-spaced intervals of time. The scheduler can provide each stream with a guaranteed real number of time-slots per time-space map, which allows for high resolution service rates to be supported without having to resort to using very large maps.

ATM service scheduler using reverse-binary scattering and time-space

A multi-stage ATM switch has a plurality of inlet stage fabrics, core stage fabrics and outlet stage fabrics. ATM cells routed by the switch have destination fields including (i) an identification of the outlet stage fabric and (ii) an identification of the outlet port. Cells incoming to a given inlet stage fabric are queued up in queues representing each of the outlet stage fabrics. A queue having at least the number of cells as there are core stage fabrics (or one having a lesser number of cells where cells have been waiting longer than an a pre-defined time) is identified and, in a time slot, cells are transmitted from the front of the identified queue, in parallel, one to each of the core stage fabrics (with blank make-up cells being sent, as necessary, where the identified queue had less cells than there are core stage fabrics). In the core stage fabrics, the incoming cells are again queued up in queues representing each of the outlet stage fabrics and then cells are transmitted from the heads of these queues to the outlet stage fabrics. At the outlet stage fabrics, incoming cells are queued in queues representing the outlet ports to which these cells are destined and cells are output from the heads of these queues.

Growing community of inventors

Kanata, Canada

Stacy W Nichols